Module lpc177x_8x::uart1

UART1

Modules

acr	Auto-baud Control Register. Contains controls for the auto-baud feature.
dll	DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.
dlm	DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.
fcr	FIFO Control Register. Controls UART1 FIFO usage and modes.
fdr	Fractional Divider Register. Generates a clock input for the baud rate divider.
ier	DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts.
iir	Interrupt ID Register. Identifies which interrupt(s) are pending.
lcr	Line Control Register. Contains controls for frame formatting and break generation.
lsr	Line Status Register. Contains flags for transmit and receive status, including line errors.
mcr	Modem Control Register. Contains controls for flow control handshaking and loopback mode.
msr	Modem Status Register. Contains handshake signal status flags.
rbr	DLAB =0 Receiver Buffer Register. Contains the next received character to be read.
rs485adrmatch	RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
rs485ctrl	RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
rs485dly	RS-485/EIA-485 direction control delay.
scr	Scratch Pad Register. 8-bit temporary storage for software.
ter	Transmit Enable Register. Turns off UART transmitter for use with software flow control.
thr	DLAB =0. Transmit Holding Register. The next character to be transmitted is written here.

Structs

ACR	Auto-baud Control Register. Contains controls for the auto-baud feature.
DLL	DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.
DLM	DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.
FCR	FIFO Control Register. Controls UART1 FIFO usage and modes.
FDR	Fractional Divider Register. Generates a clock input for the baud rate divider.
IER	DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts.
IIR	Interrupt ID Register. Identifies which interrupt(s) are pending.
LCR	Line Control Register. Contains controls for frame formatting and break generation.
LSR	Line Status Register. Contains flags for transmit and receive status, including line errors.
MCR	Modem Control Register. Contains controls for flow control handshaking and loopback mode.
MSR	Modem Status Register. Contains handshake signal status flags.
RBR	DLAB =0 Receiver Buffer Register. Contains the next received character to be read.
RS485ADRMATCH	RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
RS485CTRL	RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
RS485DLY	RS-485/EIA-485 direction control delay.
RegisterBlock	Register block
SCR	Scratch Pad Register. 8-bit temporary storage for software.
TER	Transmit Enable Register. Turns off UART transmitter for use with software flow control.
THR	DLAB =0. Transmit Holding Register. The next character to be transmitted is written here.