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/* automatically generated by rust-bindgen */

pub const _STDINT_H : u32 = 1 ; pub const _FEATURES_H : u32 = 1 ; pub const _DEFAULT_SOURCE : u32 = 1 ; pub const __USE_ISOC11 : u32 = 1 ; pub const __USE_ISOC99 : u32 = 1 ; pub const __USE_ISOC95 : u32 = 1 ; pub const __USE_POSIX_IMPLICITLY : u32 = 1 ; pub const _POSIX_SOURCE : u32 = 1 ; pub const _POSIX_C_SOURCE : u32 = 200809 ; pub const __USE_POSIX : u32 = 1 ; pub const __USE_POSIX2 : u32 = 1 ; pub const __USE_POSIX199309 : u32 = 1 ; pub const __USE_POSIX199506 : u32 = 1 ; pub const __USE_XOPEN2K : u32 = 1 ; pub const __USE_XOPEN2K8 : u32 = 1 ; pub const _ATFILE_SOURCE : u32 = 1 ; pub const __USE_MISC : u32 = 1 ; pub const __USE_ATFILE : u32 = 1 ; pub const __USE_FORTIFY_LEVEL : u32 = 0 ; pub const _STDC_PREDEF_H : u32 = 1 ; pub const __STDC_IEC_559__ : u32 = 1 ; pub const __STDC_IEC_559_COMPLEX__ : u32 = 1 ; pub const __STDC_ISO_10646__ : u32 = 201605 ; pub const __STDC_NO_THREADS__ : u32 = 1 ; pub const __GNU_LIBRARY__ : u32 = 6 ; pub const __GLIBC__ : u32 = 2 ; pub const __GLIBC_MINOR__ : u32 = 24 ; pub const _SYS_CDEFS_H : u32 = 1 ; pub const __WORDSIZE : u32 = 64 ; pub const __WORDSIZE_TIME64_COMPAT32 : u32 = 1 ; pub const __SYSCALL_WORDSIZE : u32 = 64 ; pub const _BITS_WCHAR_H : u32 = 1 ; pub const INT8_MIN : i32 = -128 ; pub const INT16_MIN : i32 = -32768 ; pub const INT32_MIN : i32 = -2147483648 ; pub const INT8_MAX : u32 = 127 ; pub const INT16_MAX : u32 = 32767 ; pub const INT32_MAX : u32 = 2147483647 ; pub const UINT8_MAX : u32 = 255 ; pub const UINT16_MAX : u32 = 65535 ; pub const UINT32_MAX : u32 = 4294967295 ; pub const INT_LEAST8_MIN : i32 = -128 ; pub const INT_LEAST16_MIN : i32 = -32768 ; pub const INT_LEAST32_MIN : i32 = -2147483648 ; pub const INT_LEAST8_MAX : u32 = 127 ; pub const INT_LEAST16_MAX : u32 = 32767 ; pub const INT_LEAST32_MAX : u32 = 2147483647 ; pub const UINT_LEAST8_MAX : u32 = 255 ; pub const UINT_LEAST16_MAX : u32 = 65535 ; pub const UINT_LEAST32_MAX : u32 = 4294967295 ; pub const INT_FAST8_MIN : i32 = -128 ; pub const INT_FAST16_MIN : i64 = -9223372036854775808 ; pub const INT_FAST32_MIN : i64 = -9223372036854775808 ; pub const INT_FAST8_MAX : u32 = 127 ; pub const INT_FAST16_MAX : u64 = 9223372036854775807 ; pub const INT_FAST32_MAX : u64 = 9223372036854775807 ; pub const UINT_FAST8_MAX : u32 = 255 ; pub const UINT_FAST16_MAX : i32 = -1 ; pub const UINT_FAST32_MAX : i32 = -1 ; pub const INTPTR_MIN : i64 = -9223372036854775808 ; pub const INTPTR_MAX : u64 = 9223372036854775807 ; pub const UINTPTR_MAX : i32 = -1 ; pub const PTRDIFF_MIN : i64 = -9223372036854775808 ; pub const PTRDIFF_MAX : u64 = 9223372036854775807 ; pub const SIG_ATOMIC_MIN : i32 = -2147483648 ; pub const SIG_ATOMIC_MAX : u32 = 2147483647 ; pub const SIZE_MAX : i32 = -1 ; pub const WINT_MIN : u32 = 0 ; pub const WINT_MAX : u32 = 4294967295 ; pub const true_ : u32 = 1 ; pub const false_ : u32 = 0 ; pub const __bool_true_false_are_defined : u32 = 1 ; pub const BIT0 : u32 = 1 ; pub const BIT1 : u32 = 2 ; pub const BIT2 : u32 = 4 ; pub const BIT3 : u32 = 8 ; pub const BIT4 : u32 = 16 ; pub const BIT5 : u32 = 32 ; pub const BIT6 : u32 = 64 ; pub const BIT7 : u32 = 128 ; pub const BIT8 : u32 = 256 ; pub const BIT9 : u32 = 512 ; pub const BIT10 : u32 = 1024 ; pub const BIT11 : u32 = 2048 ; pub const BIT12 : u32 = 4096 ; pub const BIT13 : u32 = 8192 ; pub const BIT14 : u32 = 16384 ; pub const BIT15 : u32 = 32768 ; pub const BIT16 : u32 = 65536 ; pub const BIT17 : u32 = 131072 ; pub const BIT18 : u32 = 262144 ; pub const BIT19 : u32 = 524288 ; pub const BIT20 : u32 = 1048576 ; pub const BIT21 : u32 = 2097152 ; pub const BIT22 : u32 = 4194304 ; pub const BIT23 : u32 = 8388608 ; pub const BIT24 : u32 = 16777216 ; pub const BIT25 : u32 = 33554432 ; pub const BIT26 : u32 = 67108864 ; pub const BIT27 : u32 = 134217728 ; pub const BIT28 : u32 = 268435456 ; pub const BIT29 : u32 = 536870912 ; pub const BIT30 : u32 = 1073741824 ; pub const BIT31 : u32 = 2147483648 ; pub const PPBI_BASE : u32 = 3758096384 ; pub const SCS_BASE : u32 = 3758153728 ; pub const SYS_TICK_BASE : u32 = 3758153744 ; pub const NVIC_BASE : u32 = 3758153984 ; pub const SCB_BASE : u32 = 3758157056 ; pub const MPU_BASE : u32 = 3758157200 ; pub const DWT_CTRL_NUMCOMP_SHIFT : u32 = 28 ; pub const DWT_CTRL_NUMCOMP : u32 = 4026531840 ; pub const DWT_MASKx_MASK : u32 = 15 ; pub const DWT_FUNCTIONx_MATCHED : u32 = 16777216 ; pub const DWT_FUNCTIONx_FUNCTION : u32 = 15 ; pub const DWT_FUNCTIONx_FUNCTION_DISABLED : u32 = 0 ; pub const MPU_TYPE_IREGION_LSB : u32 = 16 ; pub const MPU_TYPE_IREGION : u32 = 16711680 ; pub const MPU_TYPE_DREGION_LSB : u32 = 8 ; pub const MPU_TYPE_DREGION : u32 = 65280 ; pub const MPU_TYPE_SEPARATE : u32 = 1 ; pub const MPU_CTRL_PRIVDEFENA : u32 = 4 ; pub const MPU_CTRL_HFNMIENA : u32 = 2 ; pub const MPU_CTRL_ENABLE : u32 = 1 ; pub const MPU_RNR_REGION_LSB : u32 = 0 ; pub const MPU_RNR_REGION : u32 = 255 ; pub const MPU_RBAR_ADDR : u32 = 4294967264 ; pub const MPU_RBAR_VALID : u32 = 16 ; pub const MPU_RBAR_REGION_LSB : u32 = 0 ; pub const MPU_RBAR_REGION : u32 = 15 ; pub const MPU_RASR_ATTRS_LSB : u32 = 16 ; pub const MPU_RASR_ATTRS : u32 = 4294901760 ; pub const MPU_RASR_SRD_LSB : u32 = 8 ; pub const MPU_RASR_SRD : u32 = 65280 ; pub const MPU_RASR_SIZE_LSB : u32 = 1 ; pub const MPU_RASR_SIZE : u32 = 62 ; pub const MPU_RASR_ENABLE : u32 = 1 ; pub const MPU_RASR_ATTR_XN : u32 = 268435456 ; pub const MPU_RASR_ATTR_AP : u32 = 117440512 ; pub const MPU_RASR_ATTR_AP_PNO_UNO : u32 = 0 ; pub const MPU_RASR_ATTR_AP_PRW_UNO : u32 = 16777216 ; pub const MPU_RASR_ATTR_AP_PRW_URO : u32 = 33554432 ; pub const MPU_RASR_ATTR_AP_PRW_URW : u32 = 50331648 ; pub const MPU_RASR_ATTR_AP_PRO_UNO : u32 = 83886080 ; pub const MPU_RASR_ATTR_AP_PRO_URO : u32 = 100663296 ; pub const MPU_RASR_ATTR_TEX : u32 = 3670016 ; pub const MPU_RASR_ATTR_S : u32 = 262144 ; pub const MPU_RASR_ATTR_C : u32 = 131072 ; pub const MPU_RASR_ATTR_B : u32 = 65536 ; pub const MPU_RASR_ATTR_SCB : u32 = 458752 ; pub const NVIC_NMI_IRQ : i32 = -14 ; pub const NVIC_HARD_FAULT_IRQ : i32 = -13 ; pub const NVIC_SV_CALL_IRQ : i32 = -5 ; pub const NVIC_PENDSV_IRQ : i32 = -2 ; pub const NVIC_SYSTICK_IRQ : i32 = -1 ; pub const NVIC_WWDG_IRQ : u32 = 0 ; pub const NVIC_PVD_IRQ : u32 = 1 ; pub const NVIC_TAMPER_IRQ : u32 = 2 ; pub const NVIC_RTC_IRQ : u32 = 3 ; pub const NVIC_FLASH_IRQ : u32 = 4 ; pub const NVIC_RCC_IRQ : u32 = 5 ; pub const NVIC_EXTI0_IRQ : u32 = 6 ; pub const NVIC_EXTI1_IRQ : u32 = 7 ; pub const NVIC_EXTI2_IRQ : u32 = 8 ; pub const NVIC_EXTI3_IRQ : u32 = 9 ; pub const NVIC_EXTI4_IRQ : u32 = 10 ; pub const NVIC_DMA1_CHANNEL1_IRQ : u32 = 11 ; pub const NVIC_DMA1_CHANNEL2_IRQ : u32 = 12 ; pub const NVIC_DMA1_CHANNEL3_IRQ : u32 = 13 ; pub const NVIC_DMA1_CHANNEL4_IRQ : u32 = 14 ; pub const NVIC_DMA1_CHANNEL5_IRQ : u32 = 15 ; pub const NVIC_DMA1_CHANNEL6_IRQ : u32 = 16 ; pub const NVIC_DMA1_CHANNEL7_IRQ : u32 = 17 ; pub const NVIC_ADC1_2_IRQ : u32 = 18 ; pub const NVIC_USB_HP_CAN_TX_IRQ : u32 = 19 ; pub const NVIC_USB_LP_CAN_RX0_IRQ : u32 = 20 ; pub const NVIC_CAN_RX1_IRQ : u32 = 21 ; pub const NVIC_CAN_SCE_IRQ : u32 = 22 ; pub const NVIC_EXTI9_5_IRQ : u32 = 23 ; pub const NVIC_TIM1_BRK_IRQ : u32 = 24 ; pub const NVIC_TIM1_UP_IRQ : u32 = 25 ; pub const NVIC_TIM1_TRG_COM_IRQ : u32 = 26 ; pub const NVIC_TIM1_CC_IRQ : u32 = 27 ; pub const NVIC_TIM2_IRQ : u32 = 28 ; pub const NVIC_TIM3_IRQ : u32 = 29 ; pub const NVIC_TIM4_IRQ : u32 = 30 ; pub const NVIC_I2C1_EV_IRQ : u32 = 31 ; pub const NVIC_I2C1_ER_IRQ : u32 = 32 ; pub const NVIC_I2C2_EV_IRQ : u32 = 33 ; pub const NVIC_I2C2_ER_IRQ : u32 = 34 ; pub const NVIC_SPI1_IRQ : u32 = 35 ; pub const NVIC_SPI2_IRQ : u32 = 36 ; pub const NVIC_USART1_IRQ : u32 = 37 ; pub const NVIC_USART2_IRQ : u32 = 38 ; pub const NVIC_USART3_IRQ : u32 = 39 ; pub const NVIC_EXTI15_10_IRQ : u32 = 40 ; pub const NVIC_RTC_ALARM_IRQ : u32 = 41 ; pub const NVIC_USB_WAKEUP_IRQ : u32 = 42 ; pub const NVIC_TIM8_BRK_IRQ : u32 = 43 ; pub const NVIC_TIM8_UP_IRQ : u32 = 44 ; pub const NVIC_TIM8_TRG_COM_IRQ : u32 = 45 ; pub const NVIC_TIM8_CC_IRQ : u32 = 46 ; pub const NVIC_ADC3_IRQ : u32 = 47 ; pub const NVIC_FSMC_IRQ : u32 = 48 ; pub const NVIC_SDIO_IRQ : u32 = 49 ; pub const NVIC_TIM5_IRQ : u32 = 50 ; pub const NVIC_SPI3_IRQ : u32 = 51 ; pub const NVIC_UART4_IRQ : u32 = 52 ; pub const NVIC_UART5_IRQ : u32 = 53 ; pub const NVIC_TIM6_IRQ : u32 = 54 ; pub const NVIC_TIM7_IRQ : u32 = 55 ; pub const NVIC_DMA2_CHANNEL1_IRQ : u32 = 56 ; pub const NVIC_DMA2_CHANNEL2_IRQ : u32 = 57 ; pub const NVIC_DMA2_CHANNEL3_IRQ : u32 = 58 ; pub const NVIC_DMA2_CHANNEL4_5_IRQ : u32 = 59 ; pub const NVIC_DMA2_CHANNEL5_IRQ : u32 = 60 ; pub const NVIC_ETH_IRQ : u32 = 61 ; pub const NVIC_ETH_WKUP_IRQ : u32 = 62 ; pub const NVIC_CAN2_TX_IRQ : u32 = 63 ; pub const NVIC_CAN2_RX0_IRQ : u32 = 64 ; pub const NVIC_CAN2_RX1_IRQ : u32 = 65 ; pub const NVIC_CAN2_SCE_IRQ : u32 = 66 ; pub const NVIC_OTG_FS_IRQ : u32 = 67 ; pub const NVIC_IRQ_COUNT : u32 = 68 ; pub const SCB_CPUID_IMPLEMENTER_LSB : u32 = 24 ; pub const SCB_CPUID_IMPLEMENTER : u32 = 4278190080 ; pub const SCB_CPUID_VARIANT_LSB : u32 = 20 ; pub const SCB_CPUID_VARIANT : u32 = 15728640 ; pub const SCB_CPUID_CONSTANT_LSB : u32 = 16 ; pub const SCB_CPUID_CONSTANT : u32 = 983040 ; pub const SCB_CPUID_CONSTANT_ARMV6 : u32 = 786432 ; pub const SCB_CPUID_CONSTANT_ARMV7 : u32 = 983040 ; pub const SCB_CPUID_PARTNO_LSB : u32 = 4 ; pub const SCB_CPUID_PARTNO : u32 = 65520 ; pub const SCB_CPUID_REVISION_LSB : u32 = 0 ; pub const SCB_CPUID_REVISION : u32 = 15 ; pub const SCB_ICSR_NMIPENDSET : u32 = 2147483648 ; pub const SCB_ICSR_PENDSVSET : u32 = 268435456 ; pub const SCB_ICSR_PENDSVCLR : u32 = 134217728 ; pub const SCB_ICSR_PENDSTSET : u32 = 67108864 ; pub const SCB_ICSR_PENDSTCLR : u32 = 33554432 ; pub const SCB_ICSR_ISRPREEMPT : u32 = 8388608 ; pub const SCB_ICSR_ISRPENDING : u32 = 4194304 ; pub const SCB_ICSR_VECTPENDING_LSB : u32 = 12 ; pub const SCB_ICSR_VECTPENDING : u32 = 2093056 ; pub const SCB_ICSR_RETOBASE : u32 = 2048 ; pub const SCB_ICSR_VECTACTIVE_LSB : u32 = 0 ; pub const SCB_ICSR_VECTACTIVE : u32 = 511 ; pub const SCB_AIRCR_VECTKEYSTAT_LSB : u32 = 16 ; pub const SCB_AIRCR_VECTKEYSTAT : u32 = 4294901760 ; pub const SCB_AIRCR_VECTKEY : u32 = 100270080 ; pub const SCB_AIRCR_ENDIANESS : u32 = 32768 ; pub const SCB_AIRCR_SYSRESETREQ : u32 = 4 ; pub const SCB_AIRCR_VECTCLRACTIVE : u32 = 2 ; pub const SCB_SCR_SEVONPEND : u32 = 16 ; pub const SCB_SCR_SLEEPDEEP : u32 = 4 ; pub const SCB_SCR_SLEEPONEXIT : u32 = 2 ; pub const SCB_CCR_STKALIGN : u32 = 512 ; pub const SCB_CCR_UNALIGN_TRP : u32 = 8 ; pub const SCB_SHPR_PRI_4_MEMMANAGE : u32 = 0 ; pub const SCB_SHPR_PRI_5_BUSFAULT : u32 = 1 ; pub const SCB_SHPR_PRI_6_USAGEFAULT : u32 = 2 ; pub const SCB_SHPR_PRI_7_RESERVED : u32 = 3 ; pub const SCB_SHPR_PRI_8_RESERVED : u32 = 4 ; pub const SCB_SHPR_PRI_9_RESERVED : u32 = 5 ; pub const SCB_SHPR_PRI_10_RESERVED : u32 = 6 ; pub const SCB_SHPR_PRI_11_SVCALL : u32 = 7 ; pub const SCB_SHPR_PRI_12_RESERVED : u32 = 8 ; pub const SCB_SHPR_PRI_13_RESERVED : u32 = 9 ; pub const SCB_SHPR_PRI_14_PENDSV : u32 = 10 ; pub const SCB_SHPR_PRI_15_SYSTICK : u32 = 11 ; pub const SCB_SHCSR_SVCALLPENDED : u32 = 32768 ; pub const SCS_DHCSR_DBGKEY : u32 = 2690580480 ; pub const SCS_DHCSR_C_DEBUGEN : u32 = 1 ; pub const SCS_DHCSR_C_HALT : u32 = 2 ; pub const SCS_DHCSR_C_STEP : u32 = 4 ; pub const SCS_DHCSR_C_MASKINTS : u32 = 8 ; pub const SCS_DHCSR_C_SNAPSTALL : u32 = 32 ; pub const SCS_DHCSR_S_REGRDY : u32 = 65536 ; pub const SCS_DHCSR_S_HALT : u32 = 131072 ; pub const SCS_DHCSR_S_SLEEP : u32 = 262144 ; pub const SCS_DHCSR_S_LOCKUP : u32 = 524288 ; pub const SCS_DHCSR_S_RETIRE_ST : u32 = 16777216 ; pub const SCS_DHCSR_S_RESET_ST : u32 = 33554432 ; pub const SCS_DCRSR_REGSEL_MASK : u32 = 31 ; pub const SCS_DCRSR_REGSEL_XPSR : u32 = 16 ; pub const SCS_DCRSR_REGSEL_MSP : u32 = 17 ; pub const SCS_DCRSR_REGSEL_PSP : u32 = 18 ; pub const SCS_DEMCR_TRCENA : u32 = 16777216 ; pub const SCS_DEMCR_MON_REQ : u32 = 524288 ; pub const SCS_DEMCR_MON_STEP : u32 = 262144 ; pub const SCS_DEMCR_VC_MON_PEND : u32 = 131072 ; pub const SCS_DEMCR_VC_MON_EN : u32 = 65536 ; pub const SCS_DEMCR_VC_HARDERR : u32 = 1024 ; pub const SCS_DEMCR_VC_INTERR : u32 = 512 ; pub const SCS_DEMCR_VC_BUSERR : u32 = 256 ; pub const SCS_DEMCR_VC_STATERR : u32 = 128 ; pub const SCS_DEMCR_VC_CHKERR : u32 = 64 ; pub const SCS_DEMCR_VC_NOCPERR : u32 = 32 ; pub const SCS_DEMCR_VC_MMERR : u32 = 16 ; pub const SCS_DEMCR_VC_CORERESET : u32 = 1 ; pub const SCS_SYST_CSR_ENABLE : u32 = 1 ; pub const SCS_SYST_CSR_TICKINT : u32 = 2 ; pub const SCS_SYST_CSR_CLKSOURCE : u32 = 4 ; pub const SCS_SYST_CSR_COUNTFLAG : u32 = 65536 ; pub const SCS_SYST_SYST_CALIB_TENMS_MASK : u32 = 16777215 ; pub const SCS_SYST_SYST_CALIB_VALUE_INEXACT : u32 = 1073741824 ; pub const SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED : u32 = 2147483648 ; pub const SCS_DWT_CTRL_CYCCNTENA : u32 = 1 ; pub const SCS_LSR_SLK : u32 = 2 ; pub const SCS_LSR_SLI : u32 = 1 ; pub const SCS_LAR_KEY : u32 = 3316436565 ; pub const STK_CSR_COUNTFLAG : u32 = 65536 ; pub const STK_CSR_CLKSOURCE_LSB : u32 = 2 ; pub const STK_CSR_CLKSOURCE : u32 = 4 ; pub const STK_CSR_CLKSOURCE_AHB_DIV8 : u32 = 0 ; pub const STK_CSR_CLKSOURCE_AHB : u32 = 4 ; pub const STK_CSR_TICKINT : u32 = 2 ; pub const STK_CSR_ENABLE : u32 = 1 ; pub const STK_RVR_RELOAD : u32 = 16777215 ; pub const STK_CVR_CURRENT : u32 = 16777215 ; pub const STK_CALIB_NOREF : u32 = 2147483648 ; pub const STK_CALIB_SKEW : u32 = 1073741824 ; pub const STK_CALIB_TENMS : u32 = 16777215 ; pub const FLASH_BASE : u32 = 134217728 ; pub const PERIPH_BASE : u32 = 1073741824 ; pub const INFO_BASE : u32 = 536866816 ; pub const PERIPH_BASE_APB1 : u32 = 1073741824 ; pub const PERIPH_BASE_APB2 : u32 = 1073807360 ; pub const PERIPH_BASE_AHB : u32 = 1073840128 ; pub const TIM2_BASE : u32 = 1073741824 ; pub const TIM3_BASE : u32 = 1073742848 ; pub const TIM4_BASE : u32 = 1073743872 ; pub const TIM5_BASE : u32 = 1073744896 ; pub const TIM6_BASE : u32 = 1073745920 ; pub const TIM7_BASE : u32 = 1073746944 ; pub const TIM12_BASE : u32 = 1073747968 ; pub const TIM13_BASE : u32 = 1073748992 ; pub const TIM14_BASE : u32 = 1073750016 ; pub const RTC_BASE : u32 = 1073752064 ; pub const WWDG_BASE : u32 = 1073753088 ; pub const IWDG_BASE : u32 = 1073754112 ; pub const SPI2_BASE : u32 = 1073756160 ; pub const SPI3_BASE : u32 = 1073757184 ; pub const USART2_BASE : u32 = 1073759232 ; pub const USART3_BASE : u32 = 1073760256 ; pub const UART4_BASE : u32 = 1073761280 ; pub const UART5_BASE : u32 = 1073762304 ; pub const I2C1_BASE : u32 = 1073763328 ; pub const I2C2_BASE : u32 = 1073764352 ; pub const USB_DEV_FS_BASE : u32 = 1073765376 ; pub const USB_PMA_BASE : u32 = 1073766400 ; pub const USB_CAN_SRAM_BASE : u32 = 1073766400 ; pub const BX_CAN1_BASE : u32 = 1073767424 ; pub const BX_CAN2_BASE : u32 = 1073768448 ; pub const BACKUP_REGS_BASE : u32 = 1073769472 ; pub const POWER_CONTROL_BASE : u32 = 1073770496 ; pub const DAC_BASE : u32 = 1073771520 ; pub const CEC_BASE : u32 = 1073772544 ; pub const AFIO_BASE : u32 = 1073807360 ; pub const EXTI_BASE : u32 = 1073808384 ; pub const GPIO_PORT_A_BASE : u32 = 1073809408 ; pub const GPIO_PORT_B_BASE : u32 = 1073810432 ; pub const GPIO_PORT_C_BASE : u32 = 1073811456 ; pub const GPIO_PORT_D_BASE : u32 = 1073812480 ; pub const GPIO_PORT_E_BASE : u32 = 1073813504 ; pub const GPIO_PORT_F_BASE : u32 = 1073814528 ; pub const GPIO_PORT_G_BASE : u32 = 1073815552 ; pub const ADC1_BASE : u32 = 1073816576 ; pub const ADC2_BASE : u32 = 1073817600 ; pub const TIM1_BASE : u32 = 1073818624 ; pub const SPI1_BASE : u32 = 1073819648 ; pub const TIM8_BASE : u32 = 1073820672 ; pub const USART1_BASE : u32 = 1073821696 ; pub const ADC3_BASE : u32 = 1073822720 ; pub const TIM15_BASE : u32 = 1073823744 ; pub const TIM16_BASE : u32 = 1073824768 ; pub const TIM17_BASE : u32 = 1073825792 ; pub const TIM9_BASE : u32 = 1073826816 ; pub const TIM10_BASE : u32 = 1073827840 ; pub const TIM11_BASE : u32 = 1073828864 ; pub const SDIO_BASE : u32 = 1073840128 ; pub const DMA1_BASE : u32 = 1073872896 ; pub const DMA2_BASE : u32 = 1073873920 ; pub const RCC_BASE : u32 = 1073876992 ; pub const FLASH_MEM_INTERFACE_BASE : u32 = 1073881088 ; pub const CRC_BASE : u32 = 1073885184 ; pub const ETHERNET_BASE : u32 = 1073905664 ; pub const USB_OTG_FS_BASE : u32 = 1342177280 ; pub const DBGMCU_BASE : u32 = 3758366720 ; pub const FSMC_BASE : u32 = 2684354560 ; pub const DESIG_FLASH_SIZE_BASE : u32 = 536868832 ; pub const DESIG_UNIQUE_ID_BASE : u32 = 536868840 ; pub const ADC1 : u32 = 1073816576 ; pub const ADC2 : u32 = 1073817600 ; pub const ADC3 : u32 = 1073822720 ; pub const ADC_CHANNEL0 : u32 = 0 ; pub const ADC_CHANNEL1 : u32 = 1 ; pub const ADC_CHANNEL2 : u32 = 2 ; pub const ADC_CHANNEL3 : u32 = 3 ; pub const ADC_CHANNEL4 : u32 = 4 ; pub const ADC_CHANNEL5 : u32 = 5 ; pub const ADC_CHANNEL6 : u32 = 6 ; pub const ADC_CHANNEL7 : u32 = 7 ; pub const ADC_CHANNEL8 : u32 = 8 ; pub const ADC_CHANNEL9 : u32 = 9 ; pub const ADC_CHANNEL10 : u32 = 10 ; pub const ADC_CHANNEL11 : u32 = 11 ; pub const ADC_CHANNEL12 : u32 = 12 ; pub const ADC_CHANNEL13 : u32 = 13 ; pub const ADC_CHANNEL14 : u32 = 14 ; pub const ADC_CHANNEL15 : u32 = 15 ; pub const ADC_CHANNEL16 : u32 = 16 ; pub const ADC_CHANNEL17 : u32 = 17 ; pub const ADC_CHANNEL18 : u32 = 18 ; pub const ADC_CHANNEL_MASK : u32 = 31 ; pub const ADC_SR_STRT : u32 = 16 ; pub const ADC_SR_JSTRT : u32 = 8 ; pub const ADC_SR_JEOC : u32 = 4 ; pub const ADC_SR_EOC : u32 = 2 ; pub const ADC_SR_AWD : u32 = 1 ; pub const ADC_CR1_AWDEN : u32 = 8388608 ; pub const ADC_CR1_JAWDEN : u32 = 4194304 ; pub const ADC_CR1_DISCNUM_1CHANNELS : u32 = 0 ; pub const ADC_CR1_DISCNUM_2CHANNELS : u32 = 8192 ; pub const ADC_CR1_DISCNUM_3CHANNELS : u32 = 16384 ; pub const ADC_CR1_DISCNUM_4CHANNELS : u32 = 24576 ; pub const ADC_CR1_DISCNUM_5CHANNELS : u32 = 32768 ; pub const ADC_CR1_DISCNUM_6CHANNELS : u32 = 40960 ; pub const ADC_CR1_DISCNUM_7CHANNELS : u32 = 49152 ; pub const ADC_CR1_DISCNUM_8CHANNELS : u32 = 57344 ; pub const ADC_CR1_DISCNUM_MASK : u32 = 57344 ; pub const ADC_CR1_DISCNUM_SHIFT : u32 = 13 ; pub const ADC_CR1_JDISCEN : u32 = 4096 ; pub const ADC_CR1_DISCEN : u32 = 2048 ; pub const ADC_CR1_JAUTO : u32 = 1024 ; pub const ADC_CR1_AWDSGL : u32 = 512 ; pub const ADC_CR1_SCAN : u32 = 256 ; pub const ADC_CR1_JEOCIE : u32 = 128 ; pub const ADC_CR1_AWDIE : u32 = 64 ; pub const ADC_CR1_EOCIE : u32 = 32 ; pub const ADC_CR1_AWDCH_CHANNEL0 : u32 = 0 ; pub const ADC_CR1_AWDCH_CHANNEL1 : u32 = 1 ; pub const ADC_CR1_AWDCH_CHANNEL2 : u32 = 2 ; pub const ADC_CR1_AWDCH_CHANNEL3 : u32 = 3 ; pub const ADC_CR1_AWDCH_CHANNEL4 : u32 = 4 ; pub const ADC_CR1_AWDCH_CHANNEL5 : u32 = 5 ; pub const ADC_CR1_AWDCH_CHANNEL6 : u32 = 6 ; pub const ADC_CR1_AWDCH_CHANNEL7 : u32 = 7 ; pub const ADC_CR1_AWDCH_CHANNEL8 : u32 = 8 ; pub const ADC_CR1_AWDCH_CHANNEL9 : u32 = 9 ; pub const ADC_CR1_AWDCH_CHANNEL10 : u32 = 10 ; pub const ADC_CR1_AWDCH_CHANNEL11 : u32 = 11 ; pub const ADC_CR1_AWDCH_CHANNEL12 : u32 = 12 ; pub const ADC_CR1_AWDCH_CHANNEL13 : u32 = 13 ; pub const ADC_CR1_AWDCH_CHANNEL14 : u32 = 14 ; pub const ADC_CR1_AWDCH_CHANNEL15 : u32 = 15 ; pub const ADC_CR1_AWDCH_CHANNEL16 : u32 = 16 ; pub const ADC_CR1_AWDCH_CHANNEL17 : u32 = 17 ; pub const ADC_CR1_AWDCH_MASK : u32 = 31 ; pub const ADC_CR1_AWDCH_SHIFT : u32 = 0 ; pub const ADC_CR2_ALIGN_RIGHT : u32 = 0 ; pub const ADC_CR2_ALIGN_LEFT : u32 = 2048 ; pub const ADC_CR2_ALIGN : u32 = 2048 ; pub const ADC_CR2_DMA : u32 = 256 ; pub const ADC_CR2_CONT : u32 = 2 ; pub const ADC_CR2_ADON : u32 = 1 ; pub const ADC_JOFFSET_LSB : u32 = 0 ; pub const ADC_JOFFSET_MSK : u32 = 4095 ; pub const ADC_HT_LSB : u32 = 0 ; pub const ADC_HT_MSK : u32 = 4095 ; pub const ADC_LT_LSB : u32 = 0 ; pub const ADC_LT_MSK : u32 = 4095 ; pub const ADC_SQR1_L_LSB : u32 = 20 ; pub const ADC_JSQR_JL_LSB : u32 = 20 ; pub const ADC_JSQR_JSQ4_LSB : u32 = 15 ; pub const ADC_JSQR_JSQ3_LSB : u32 = 10 ; pub const ADC_JSQR_JSQ2_LSB : u32 = 5 ; pub const ADC_JSQR_JSQ1_LSB : u32 = 0 ; pub const ADC_JSQR_JL_1CHANNELS : u32 = 0 ; pub const ADC_JSQR_JL_2CHANNELS : u32 = 1048576 ; pub const ADC_JSQR_JL_3CHANNELS : u32 = 2097152 ; pub const ADC_JSQR_JL_4CHANNELS : u32 = 3145728 ; pub const ADC_JSQR_JL_MSK : u32 = 2097152 ; pub const ADC_JSQR_JSQ4_MSK : u32 = 1015808 ; pub const ADC_JSQR_JSQ3_MSK : u32 = 31744 ; pub const ADC_JSQR_JSQ2_MSK : u32 = 992 ; pub const ADC_JSQR_JSQ1_MSK : u32 = 31 ; pub const ADC_CR1_DUALMOD_IND : u32 = 0 ; pub const ADC_CR1_DUALMOD_CRSISM : u32 = 65536 ; pub const ADC_CR1_DUALMOD_CRSATM : u32 = 131072 ; pub const ADC_CR1_DUALMOD_CISFIM : u32 = 196608 ; pub const ADC_CR1_DUALMOD_CISSIM : u32 = 262144 ; pub const ADC_CR1_DUALMOD_ISM : u32 = 327680 ; pub const ADC_CR1_DUALMOD_RSM : u32 = 393216 ; pub const ADC_CR1_DUALMOD_FIM : u32 = 458752 ; pub const ADC_CR1_DUALMOD_SIM : u32 = 524288 ; pub const ADC_CR1_DUALMOD_ATM : u32 = 589824 ; pub const ADC_CR1_DUALMOD_MASK : u32 = 983040 ; pub const ADC_CR1_DUALMOD_SHIFT : u32 = 16 ; pub const ADC_CR1_AWDCH_MAX : u32 = 17 ; pub const ADC_CR2_TSVREFE : u32 = 8388608 ; pub const ADC_CR2_SWSTART : u32 = 4194304 ; pub const ADC_CR2_JSWSTART : u32 = 2097152 ; pub const ADC_CR2_EXTTRIG : u32 = 1048576 ; pub const ADC_CR2_EXTSEL_TIM1_CC1 : u32 = 0 ; pub const ADC_CR2_EXTSEL_TIM1_CC2 : u32 = 131072 ; pub const ADC_CR2_EXTSEL_TIM1_CC3 : u32 = 262144 ; pub const ADC_CR2_EXTSEL_TIM2_CC2 : u32 = 393216 ; pub const ADC_CR2_EXTSEL_TIM3_TRGO : u32 = 524288 ; pub const ADC_CR2_EXTSEL_TIM4_CC4 : u32 = 655360 ; pub const ADC_CR2_EXTSEL_EXTI11 : u32 = 786432 ; pub const ADC_CR2_EXTSEL_SWSTART : u32 = 917504 ; pub const ADC_CR2_EXTSEL_TIM3_CC1 : u32 = 0 ; pub const ADC_CR2_EXTSEL_TIM2_CC3 : u32 = 131072 ; pub const ADC_CR2_EXTSEL_TIM8_CC1 : u32 = 393216 ; pub const ADC_CR2_EXTSEL_TIM8_TRGO : u32 = 524288 ; pub const ADC_CR2_EXTSEL_TIM5_CC1 : u32 = 655360 ; pub const ADC_CR2_EXTSEL_TIM5_CC3 : u32 = 786432 ; pub const ADC_CR2_EXTSEL_MASK : u32 = 917504 ; pub const ADC_CR2_EXTSEL_SHIFT : u32 = 17 ; pub const ADC_CR2_JEXTTRIG : u32 = 32768 ; pub const ADC_CR2_JEXTSEL_TIM1_TRGO : u32 = 0 ; pub const ADC_CR2_JEXTSEL_TIM1_CC4 : u32 = 4096 ; pub const ADC_CR2_JEXTSEL_TIM2_TRGO : u32 = 8192 ; pub const ADC_CR2_JEXTSEL_TIM2_CC1 : u32 = 12288 ; pub const ADC_CR2_JEXTSEL_TIM3_CC4 : u32 = 16384 ; pub const ADC_CR2_JEXTSEL_TIM4_TRGO : u32 = 20480 ; pub const ADC_CR2_JEXTSEL_EXTI15 : u32 = 24576 ; pub const ADC_CR2_JEXTSEL_JSWSTART : u32 = 28672 ; pub const ADC_CR2_JEXTSEL_TIM4_CC3 : u32 = 8192 ; pub const ADC_CR2_JEXTSEL_TIM8_CC2 : u32 = 12288 ; pub const ADC_CR2_JEXTSEL_TIM8_CC4 : u32 = 16384 ; pub const ADC_CR2_JEXTSEL_TIM5_TRGO : u32 = 20480 ; pub const ADC_CR2_JEXTSEL_TIM5_CC4 : u32 = 24576 ; pub const ADC_CR2_JEXTSEL_MASK : u32 = 28672 ; pub const ADC_CR2_JEXTSEL_SHIFT : u32 = 12 ; pub const ADC_CR2_RSTCAL : u32 = 8 ; pub const ADC_CR2_CAL : u32 = 4 ; pub const ADC_SMPR1_SMP17_LSB : u32 = 21 ; pub const ADC_SMPR1_SMP16_LSB : u32 = 18 ; pub const ADC_SMPR1_SMP15_LSB : u32 = 15 ; pub const ADC_SMPR1_SMP14_LSB : u32 = 12 ; pub const ADC_SMPR1_SMP13_LSB : u32 = 9 ; pub const ADC_SMPR1_SMP12_LSB : u32 = 6 ; pub const ADC_SMPR1_SMP11_LSB : u32 = 3 ; pub const ADC_SMPR1_SMP10_LSB : u32 = 0 ; pub const ADC_SMPR1_SMP17_MSK : u32 = 14680064 ; pub const ADC_SMPR1_SMP16_MSK : u32 = 1835008 ; pub const ADC_SMPR1_SMP15_MSK : u32 = 229376 ; pub const ADC_SMPR1_SMP14_MSK : u32 = 28672 ; pub const ADC_SMPR1_SMP13_MSK : u32 = 3584 ; pub const ADC_SMPR1_SMP12_MSK : u32 = 448 ; pub const ADC_SMPR1_SMP11_MSK : u32 = 56 ; pub const ADC_SMPR1_SMP10_MSK : u32 = 7 ; pub const ADC_SMPR2_SMP9_LSB : u32 = 27 ; pub const ADC_SMPR2_SMP8_LSB : u32 = 24 ; pub const ADC_SMPR2_SMP7_LSB : u32 = 21 ; pub const ADC_SMPR2_SMP6_LSB : u32 = 18 ; pub const ADC_SMPR2_SMP5_LSB : u32 = 15 ; pub const ADC_SMPR2_SMP4_LSB : u32 = 12 ; pub const ADC_SMPR2_SMP3_LSB : u32 = 9 ; pub const ADC_SMPR2_SMP2_LSB : u32 = 6 ; pub const ADC_SMPR2_SMP1_LSB : u32 = 3 ; pub const ADC_SMPR2_SMP0_LSB : u32 = 0 ; pub const ADC_SMPR2_SMP9_MSK : u32 = 939524096 ; pub const ADC_SMPR2_SMP8_MSK : u32 = 117440512 ; pub const ADC_SMPR2_SMP7_MSK : u32 = 14680064 ; pub const ADC_SMPR2_SMP6_MSK : u32 = 1835008 ; pub const ADC_SMPR2_SMP5_MSK : u32 = 229376 ; pub const ADC_SMPR2_SMP4_MSK : u32 = 28672 ; pub const ADC_SMPR2_SMP3_MSK : u32 = 3584 ; pub const ADC_SMPR2_SMP2_MSK : u32 = 448 ; pub const ADC_SMPR2_SMP1_MSK : u32 = 56 ; pub const ADC_SMPR2_SMP0_MSK : u32 = 7 ; pub const ADC_SMPR_SMP_1DOT5CYC : u32 = 0 ; pub const ADC_SMPR_SMP_7DOT5CYC : u32 = 1 ; pub const ADC_SMPR_SMP_13DOT5CYC : u32 = 2 ; pub const ADC_SMPR_SMP_28DOT5CYC : u32 = 3 ; pub const ADC_SMPR_SMP_41DOT5CYC : u32 = 4 ; pub const ADC_SMPR_SMP_55DOT5CYC : u32 = 5 ; pub const ADC_SMPR_SMP_71DOT5CYC : u32 = 6 ; pub const ADC_SMPR_SMP_239DOT5CYC : u32 = 7 ; pub const ADC_SQR_MAX_CHANNELS_REGULAR : u32 = 16 ; pub const ADC_SQR1_SQ16_LSB : u32 = 15 ; pub const ADC_SQR1_SQ15_LSB : u32 = 10 ; pub const ADC_SQR1_SQ14_LSB : u32 = 5 ; pub const ADC_SQR1_SQ13_LSB : u32 = 0 ; pub const ADC_SQR1_L_MSK : u32 = 15728640 ; pub const ADC_SQR1_SQ16_MSK : u32 = 1015808 ; pub const ADC_SQR1_SQ15_MSK : u32 = 31744 ; pub const ADC_SQR1_SQ14_MSK : u32 = 992 ; pub const ADC_SQR1_SQ13_MSK : u32 = 31 ; pub const ADC_SQR2_SQ12_LSB : u32 = 25 ; pub const ADC_SQR2_SQ11_LSB : u32 = 20 ; pub const ADC_SQR2_SQ10_LSB : u32 = 15 ; pub const ADC_SQR2_SQ9_LSB : u32 = 10 ; pub const ADC_SQR2_SQ8_LSB : u32 = 5 ; pub const ADC_SQR2_SQ7_LSB : u32 = 0 ; pub const ADC_SQR2_SQ12_MSK : u32 = 1040187392 ; pub const ADC_SQR2_SQ11_MSK : u32 = 32505856 ; pub const ADC_SQR2_SQ10_MSK : u32 = 1015808 ; pub const ADC_SQR2_SQ9_MSK : u32 = 31744 ; pub const ADC_SQR2_SQ8_MSK : u32 = 992 ; pub const ADC_SQR2_SQ7_MSK : u32 = 31 ; pub const ADC_SQR3_SQ6_LSB : u32 = 25 ; pub const ADC_SQR3_SQ5_LSB : u32 = 20 ; pub const ADC_SQR3_SQ4_LSB : u32 = 15 ; pub const ADC_SQR3_SQ3_LSB : u32 = 10 ; pub const ADC_SQR3_SQ2_LSB : u32 = 5 ; pub const ADC_SQR3_SQ1_LSB : u32 = 0 ; pub const ADC_SQR3_SQ6_MSK : u32 = 1040187392 ; pub const ADC_SQR3_SQ5_MSK : u32 = 32505856 ; pub const ADC_SQR3_SQ4_MSK : u32 = 1015808 ; pub const ADC_SQR3_SQ3_MSK : u32 = 31744 ; pub const ADC_SQR3_SQ2_MSK : u32 = 992 ; pub const ADC_SQR3_SQ1_MSK : u32 = 31 ; pub const ADC_JDATA_LSB : u32 = 0 ; pub const ADC_DATA_LSB : u32 = 0 ; pub const ADC_ADC2DATA_LSB : u32 = 16 ; pub const ADC_JDATA_MSK : u32 = 65535 ; pub const ADC_ADC2DATA_MSK : u32 = 4294901760 ; pub const ADC_CHANNEL_TEMP : u32 = 16 ; pub const ADC_CHANNEL_VREF : u32 = 17 ; pub const CAN1 : u32 = 1073767424 ; pub const CAN2 : u32 = 1073768448 ; pub const CAN_MBOX0 : u32 = 384 ; pub const CAN_MBOX1 : u32 = 400 ; pub const CAN_MBOX2 : u32 = 416 ; pub const CAN_FIFO0 : u32 = 432 ; pub const CAN_FIFO1 : u32 = 448 ; pub const CAN_MCR_DBF : u32 = 65536 ; pub const CAN_MCR_RESET : u32 = 32768 ; pub const CAN_MCR_TTCM : u32 = 128 ; pub const CAN_MCR_ABOM : u32 = 64 ; pub const CAN_MCR_AWUM : u32 = 32 ; pub const CAN_MCR_NART : u32 = 16 ; pub const CAN_MCR_RFLM : u32 = 8 ; pub const CAN_MCR_TXFP : u32 = 4 ; pub const CAN_MCR_SLEEP : u32 = 2 ; pub const CAN_MCR_INRQ : u32 = 1 ; pub const CAN_MSR_RX : u32 = 2048 ; pub const CAN_MSR_SAMP : u32 = 1024 ; pub const CAN_MSR_RXM : u32 = 512 ; pub const CAN_MSR_TXM : u32 = 256 ; pub const CAN_MSR_SLAKI : u32 = 16 ; pub const CAN_MSR_WKUI : u32 = 8 ; pub const CAN_MSR_ERRI : u32 = 4 ; pub const CAN_MSR_SLAK : u32 = 2 ; pub const CAN_MSR_INAK : u32 = 1 ; pub const CAN_TSR_LOW2 : u32 = 2147483648 ; pub const CAN_TSR_LOW1 : u32 = 1073741824 ; pub const CAN_TSR_LOW0 : u32 = 536870912 ; pub const CAN_TSR_TME2 : u32 = 268435456 ; pub const CAN_TSR_TME1 : u32 = 134217728 ; pub const CAN_TSR_TME0 : u32 = 67108864 ; pub const CAN_TSR_CODE_MASK : u32 = 50331648 ; pub const CAN_TSR_ABRQ2 : u32 = 8388608 ; pub const CAN_TSR_TERR2 : u32 = 524288 ; pub const CAN_TSR_ALST2 : u32 = 262144 ; pub const CAN_TSR_TXOK2 : u32 = 131072 ; pub const CAN_TSR_RQCP2 : u32 = 65536 ; pub const CAN_TSR_ABRQ1 : u32 = 32768 ; pub const CAN_TSR_TERR1 : u32 = 2048 ; pub const CAN_TSR_ALST1 : u32 = 1024 ; pub const CAN_TSR_TXOK1 : u32 = 512 ; pub const CAN_TSR_RQCP1 : u32 = 256 ; pub const CAN_TSR_ABRQ0 : u32 = 128 ; pub const CAN_TSR_TERR0 : u32 = 8 ; pub const CAN_TSR_ALST0 : u32 = 4 ; pub const CAN_TSR_TXOK0 : u32 = 2 ; pub const CAN_TSR_RQCP0 : u32 = 1 ; pub const CAN_RF0R_RFOM0 : u32 = 32 ; pub const CAN_RF0R_FOVR0 : u32 = 16 ; pub const CAN_RF0R_FULL0 : u32 = 8 ; pub const CAN_RF0R_FMP0_MASK : u32 = 3 ; pub const CAN_RF1R_RFOM1 : u32 = 32 ; pub const CAN_RF1R_FOVR1 : u32 = 16 ; pub const CAN_RF1R_FULL1 : u32 = 8 ; pub const CAN_RF1R_FMP1_MASK : u32 = 3 ; pub const CAN_IER_SLKIE : u32 = 131072 ; pub const CAN_IER_WKUIE : u32 = 65536 ; pub const CAN_IER_ERRIE : u32 = 32768 ; pub const CAN_IER_LECIE : u32 = 2048 ; pub const CAN_IER_BOFIE : u32 = 1024 ; pub const CAN_IER_EPVIE : u32 = 512 ; pub const CAN_IER_EWGIE : u32 = 256 ; pub const CAN_IER_FOVIE1 : u32 = 64 ; pub const CAN_IER_FFIE1 : u32 = 32 ; pub const CAN_IER_FMPIE1 : u32 = 16 ; pub const CAN_IER_FOVIE0 : u32 = 8 ; pub const CAN_IER_FFIE0 : u32 = 4 ; pub const CAN_IER_FMPIE0 : u32 = 2 ; pub const CAN_IER_TMEIE : u32 = 1 ; pub const CAN_ESR_REC_MASK : u32 = 251658240 ; pub const CAN_ESR_TEC_MASK : u32 = 983040 ; pub const CAN_ESR_LEC_NO_ERROR : u32 = 0 ; pub const CAN_ESR_LEC_STUFF_ERROR : u32 = 16 ; pub const CAN_ESR_LEC_FORM_ERROR : u32 = 32 ; pub const CAN_ESR_LEC_ACK_ERROR : u32 = 48 ; pub const CAN_ESR_LEC_REC_ERROR : u32 = 64 ; pub const CAN_ESR_LEC_DOM_ERROR : u32 = 80 ; pub const CAN_ESR_LEC_CRC_ERROR : u32 = 96 ; pub const CAN_ESR_LEC_SOFT_ERROR : u32 = 112 ; pub const CAN_ESR_LEC_MASK : u32 = 112 ; pub const CAN_ESR_BOFF : u32 = 4 ; pub const CAN_ESR_EPVF : u32 = 2 ; pub const CAN_ESR_EWGF : u32 = 1 ; pub const CAN_BTR_SILM : u32 = 2147483648 ; pub const CAN_BTR_LBKM : u32 = 1073741824 ; pub const CAN_BTR_SJW_1TQ : u32 = 0 ; pub const CAN_BTR_SJW_2TQ : u32 = 16777216 ; pub const CAN_BTR_SJW_3TQ : u32 = 33554432 ; pub const CAN_BTR_SJW_4TQ : u32 = 50331648 ; pub const CAN_BTR_SJW_MASK : u32 = 50331648 ; pub const CAN_BTR_SJW_SHIFT : u32 = 24 ; pub const CAN_BTR_TS2_1TQ : u32 = 0 ; pub const CAN_BTR_TS2_2TQ : u32 = 1048576 ; pub const CAN_BTR_TS2_3TQ : u32 = 2097152 ; pub const CAN_BTR_TS2_4TQ : u32 = 3145728 ; pub const CAN_BTR_TS2_5TQ : u32 = 4194304 ; pub const CAN_BTR_TS2_6TQ : u32 = 5242880 ; pub const CAN_BTR_TS2_7TQ : u32 = 6291456 ; pub const CAN_BTR_TS2_8TQ : u32 = 7340032 ; pub const CAN_BTR_TS2_MASK : u32 = 7340032 ; pub const CAN_BTR_TS2_SHIFT : u32 = 20 ; pub const CAN_BTR_TS1_1TQ : u32 = 0 ; pub const CAN_BTR_TS1_2TQ : u32 = 65536 ; pub const CAN_BTR_TS1_3TQ : u32 = 131072 ; pub const CAN_BTR_TS1_4TQ : u32 = 196608 ; pub const CAN_BTR_TS1_5TQ : u32 = 262144 ; pub const CAN_BTR_TS1_6TQ : u32 = 327680 ; pub const CAN_BTR_TS1_7TQ : u32 = 393216 ; pub const CAN_BTR_TS1_8TQ : u32 = 458752 ; pub const CAN_BTR_TS1_9TQ : u32 = 524288 ; pub const CAN_BTR_TS1_10TQ : u32 = 589824 ; pub const CAN_BTR_TS1_11TQ : u32 = 655360 ; pub const CAN_BTR_TS1_12TQ : u32 = 720896 ; pub const CAN_BTR_TS1_13TQ : u32 = 786432 ; pub const CAN_BTR_TS1_14TQ : u32 = 851968 ; pub const CAN_BTR_TS1_15TQ : u32 = 917504 ; pub const CAN_BTR_TS1_16TQ : u32 = 983040 ; pub const CAN_BTR_TS1_MASK : u32 = 983040 ; pub const CAN_BTR_TS1_SHIFT : u32 = 16 ; pub const CAN_BTR_BRP_MASK : u32 = 1023 ; pub const CAN_TIxR_STID_MASK : u32 = 4292870144 ; pub const CAN_TIxR_STID_SHIFT : u32 = 21 ; pub const CAN_TIxR_EXID_MASK : u32 = 268435448 ; pub const CAN_TIxR_EXID_SHIFT : u32 = 3 ; pub const CAN_TIxR_IDE : u32 = 4 ; pub const CAN_TIxR_RTR : u32 = 2 ; pub const CAN_TIxR_TXRQ : u32 = 1 ; pub const CAN_TDTxR_TIME_MASK : u32 = 2147450880 ; pub const CAN_TDTxR_TIME_SHIFT : u32 = 15 ; pub const CAN_TDTxR_TGT : u32 = 32 ; pub const CAN_TDTxR_DLC_MASK : u32 = 15 ; pub const CAN_TDTxR_DLC_SHIFT : u32 = 0 ; pub const CAN_RIxR_STID_MASK : u32 = 2047 ; pub const CAN_RIxR_STID_SHIFT : u32 = 21 ; pub const CAN_RIxR_EXID_MASK : u32 = 536870911 ; pub const CAN_RIxR_EXID_SHIFT : u32 = 3 ; pub const CAN_RIxR_IDE : u32 = 4 ; pub const CAN_RIxR_RTR : u32 = 2 ; pub const CAN_RDTxR_TIME_MASK : u32 = 4294901760 ; pub const CAN_RDTxR_TIME_SHIFT : u32 = 16 ; pub const CAN_RDTxR_FMI_MASK : u32 = 65280 ; pub const CAN_RDTxR_FMI_SHIFT : u32 = 8 ; pub const CAN_RDTxR_DLC_MASK : u32 = 15 ; pub const CAN_RDTxR_DLC_SHIFT : u32 = 0 ; pub const CAN_FMR_CAN2SB_SHIFT : u32 = 8 ; pub const CAN_FMR_CAN2SB_MASK : u32 = 16128 ; pub const CAN_FMR_FINIT : u32 = 1 ; pub const CRC_CR_RESET : u32 = 1 ; pub const DAC_CR_DMAUDRIE2 : u32 = 536870912 ; pub const DAC_CR_DMAEN2 : u32 = 268435456 ; pub const DAC_CR_MAMP2_SHIFT : u32 = 24 ; pub const DAC_CR_MAMP2_1 : u32 = 0 ; pub const DAC_CR_MAMP2_2 : u32 = 16777216 ; pub const DAC_CR_MAMP2_3 : u32 = 33554432 ; pub const DAC_CR_MAMP2_4 : u32 = 50331648 ; pub const DAC_CR_MAMP2_5 : u32 = 67108864 ; pub const DAC_CR_MAMP2_6 : u32 = 83886080 ; pub const DAC_CR_MAMP2_7 : u32 = 100663296 ; pub const DAC_CR_MAMP2_8 : u32 = 117440512 ; pub const DAC_CR_MAMP2_9 : u32 = 134217728 ; pub const DAC_CR_MAMP2_10 : u32 = 150994944 ; pub const DAC_CR_MAMP2_11 : u32 = 167772160 ; pub const DAC_CR_MAMP2_12 : u32 = 184549376 ; pub const DAC_CR_WAVE2_SHIFT : u32 = 22 ; pub const DAC_CR_WAVE2_DIS : u32 = 12582912 ; pub const DAC_CR_WAVE2_NOISE : u32 = 4194304 ; pub const DAC_CR_WAVE2_TRI : u32 = 8388608 ; pub const DAC_CR_TSEL2_SHIFT : u32 = 19 ; pub const DAC_CR_TSEL2_T6 : u32 = 0 ; pub const DAC_CR_TSEL2_T3 : u32 = 524288 ; pub const DAC_CR_TSEL2_T8 : u32 = 524288 ; pub const DAC_CR_TSEL2_T7 : u32 = 1048576 ; pub const DAC_CR_TSEL2_T5 : u32 = 1572864 ; pub const DAC_CR_TSEL2_T15 : u32 = 1572864 ; pub const DAC_CR_TSEL2_T2 : u32 = 2097152 ; pub const DAC_CR_TSEL2_T4 : u32 = 2621440 ; pub const DAC_CR_TSEL2_E9 : u32 = 3145728 ; pub const DAC_CR_TSEL2_SW : u32 = 3670016 ; pub const DAC_CR_TEN2 : u32 = 262144 ; pub const DAC_CR_BOFF2 : u32 = 131072 ; pub const DAC_CR_EN2 : u32 = 65536 ; pub const DAC_CR_DMAUDRIE1 : u32 = 8192 ; pub const DAC_CR_DMAEN1 : u32 = 4096 ; pub const DAC_CR_MAMP1_SHIFT : u32 = 8 ; pub const DAC_CR_MAMP1_1 : u32 = 0 ; pub const DAC_CR_MAMP1_2 : u32 = 256 ; pub const DAC_CR_MAMP1_3 : u32 = 512 ; pub const DAC_CR_MAMP1_4 : u32 = 768 ; pub const DAC_CR_MAMP1_5 : u32 = 1024 ; pub const DAC_CR_MAMP1_6 : u32 = 1280 ; pub const DAC_CR_MAMP1_7 : u32 = 1536 ; pub const DAC_CR_MAMP1_8 : u32 = 1792 ; pub const DAC_CR_MAMP1_9 : u32 = 2048 ; pub const DAC_CR_MAMP1_10 : u32 = 2304 ; pub const DAC_CR_MAMP1_11 : u32 = 2560 ; pub const DAC_CR_MAMP1_12 : u32 = 2816 ; pub const DAC_CR_WAVE1_SHIFT : u32 = 6 ; pub const DAC_CR_WAVE1_DIS : u32 = 192 ; pub const DAC_CR_WAVE1_NOISE : u32 = 64 ; pub const DAC_CR_WAVE1_TRI : u32 = 128 ; pub const DAC_CR_TSEL1_SHIFT : u32 = 3 ; pub const DAC_CR_TSEL1_T6 : u32 = 0 ; pub const DAC_CR_TSEL1_T3 : u32 = 8 ; pub const DAC_CR_TSEL1_T8 : u32 = 8 ; pub const DAC_CR_TSEL1_T7 : u32 = 16 ; pub const DAC_CR_TSEL1_T5 : u32 = 24 ; pub const DAC_CR_TSEL1_T15 : u32 = 24 ; pub const DAC_CR_TSEL1_T2 : u32 = 32 ; pub const DAC_CR_TSEL1_T4 : u32 = 40 ; pub const DAC_CR_TSEL1_E9 : u32 = 48 ; pub const DAC_CR_TSEL1_SW : u32 = 56 ; pub const DAC_CR_TEN1 : u32 = 4 ; pub const DAC_CR_BOFF1 : u32 = 2 ; pub const DAC_CR_EN1 : u32 = 1 ; pub const DAC_SWTRIGR_SWTRIG2 : u32 = 2 ; pub const DAC_SWTRIGR_SWTRIG1 : u32 = 1 ; pub const DAC_DHR12R1_DACC1DHR_LSB : u32 = 1 ; pub const DAC_DHR12R1_DACC1DHR_MSK : u32 = 4095 ; pub const DAC_DHR12L1_DACC1DHR_LSB : u32 = 16 ; pub const DAC_DHR12L1_DACC1DHR_MSK : u32 = 65520 ; pub const DAC_DHR8R1_DACC1DHR_LSB : u32 = 1 ; pub const DAC_DHR8R1_DACC1DHR_MSK : u32 = 255 ; pub const DAC_DHR12R2_DACC2DHR_LSB : u32 = 1 ; pub const DAC_DHR12R2_DACC2DHR_MSK : u32 = 4095 ; pub const DAC_DHR12L2_DACC2DHR_LSB : u32 = 16 ; pub const DAC_DHR12L2_DACC2DHR_MSK : u32 = 65520 ; pub const DAC_DHR8R2_DACC2DHR_LSB : u32 = 1 ; pub const DAC_DHR8R2_DACC2DHR_MSK : u32 = 255 ; pub const DAC_DHR12RD_DACC2DHR_LSB : u32 = 65536 ; pub const DAC_DHR12RD_DACC2DHR_MSK : u32 = 268369920 ; pub const DAC_DHR12RD_DACC1DHR_LSB : u32 = 1 ; pub const DAC_DHR12RD_DACC1DHR_MSK : u32 = 4095 ; pub const DAC_DHR12LD_DACC2DHR_LSB : u32 = 65536 ; pub const DAC_DHR12LD_DACC2DHR_MSK : u32 = 4293918720 ; pub const DAC_DHR12LD_DACC1DHR_LSB : u32 = 1 ; pub const DAC_DHR12LD_DACC1DHR_MSK : u32 = 65520 ; pub const DAC_DHR8RD_DACC2DHR_LSB : u32 = 256 ; pub const DAC_DHR8RD_DACC2DHR_MSK : u32 = 65280 ; pub const DAC_DHR8RD_DACC1DHR_LSB : u32 = 1 ; pub const DAC_DHR8RD_DACC1DHR_MSK : u32 = 255 ; pub const DAC_DOR1_DACC1DOR_LSB : u32 = 1 ; pub const DAC_DOR1_DACC1DOR_MSK : u32 = 4095 ; pub const DAC_DOR2_DACC2DOR_LSB : u32 = 1 ; pub const DAC_DOR2_DACC2DOR_MSK : u32 = 4095 ; pub const DMA1 : u32 = 1073872896 ; pub const DMA2 : u32 = 1073873920 ; pub const DMA_TEIF : u32 = 8 ; pub const DMA_HTIF : u32 = 4 ; pub const DMA_TCIF : u32 = 2 ; pub const DMA_GIF : u32 = 1 ; pub const DMA_FLAGS : u32 = 15 ; pub const DMA_ISR_TEIF_BIT : u32 = 8 ; pub const DMA_ISR_HTIF_BIT : u32 = 4 ; pub const DMA_ISR_TCIF_BIT : u32 = 2 ; pub const DMA_ISR_GIF_BIT : u32 = 1 ; pub const DMA_IFCR_CTEIF_BIT : u32 = 8 ; pub const DMA_IFCR_CHTIF_BIT : u32 = 4 ; pub const DMA_IFCR_CTCIF_BIT : u32 = 2 ; pub const DMA_IFCR_CGIF_BIT : u32 = 1 ; pub const DMA_IFCR_CIF_BIT : u32 = 15 ; pub const DMA_CCR_MEM2MEM : u32 = 16384 ; pub const DMA_CCR_PL_LOW : u32 = 0 ; pub const DMA_CCR_PL_MEDIUM : u32 = 4096 ; pub const DMA_CCR_PL_HIGH : u32 = 8192 ; pub const DMA_CCR_PL_VERY_HIGH : u32 = 12288 ; pub const DMA_CCR_PL_MASK : u32 = 12288 ; pub const DMA_CCR_PL_SHIFT : u32 = 12 ; pub const DMA_CCR_MSIZE_8BIT : u32 = 0 ; pub const DMA_CCR_MSIZE_16BIT : u32 = 1024 ; pub const DMA_CCR_MSIZE_32BIT : u32 = 2048 ; pub const DMA_CCR_MSIZE_MASK : u32 = 3072 ; pub const DMA_CCR_MSIZE_SHIFT : u32 = 10 ; pub const DMA_CCR_PSIZE_8BIT : u32 = 0 ; pub const DMA_CCR_PSIZE_16BIT : u32 = 256 ; pub const DMA_CCR_PSIZE_32BIT : u32 = 512 ; pub const DMA_CCR_PSIZE_MASK : u32 = 768 ; pub const DMA_CCR_PSIZE_SHIFT : u32 = 8 ; pub const DMA_CCR_MINC : u32 = 128 ; pub const DMA_CCR_PINC : u32 = 64 ; pub const DMA_CCR_CIRC : u32 = 32 ; pub const DMA_CCR_DIR : u32 = 16 ; pub const DMA_CCR_TEIE : u32 = 8 ; pub const DMA_CCR_HTIE : u32 = 4 ; pub const DMA_CCR_TCIE : u32 = 2 ; pub const DMA_CCR_EN : u32 = 1 ; pub const DMA_CHANNEL1 : u32 = 1 ; pub const DMA_CHANNEL2 : u32 = 2 ; pub const DMA_CHANNEL3 : u32 = 3 ; pub const DMA_CHANNEL4 : u32 = 4 ; pub const DMA_CHANNEL5 : u32 = 5 ; pub const DMA_CHANNEL6 : u32 = 6 ; pub const DMA_CHANNEL7 : u32 = 7 ; pub const EXTI0 : u32 = 1 ; pub const EXTI1 : u32 = 2 ; pub const EXTI2 : u32 = 4 ; pub const EXTI3 : u32 = 8 ; pub const EXTI4 : u32 = 16 ; pub const EXTI5 : u32 = 32 ; pub const EXTI6 : u32 = 64 ; pub const EXTI7 : u32 = 128 ; pub const EXTI8 : u32 = 256 ; pub const EXTI9 : u32 = 512 ; pub const EXTI10 : u32 = 1024 ; pub const EXTI11 : u32 = 2048 ; pub const EXTI12 : u32 = 4096 ; pub const EXTI13 : u32 = 8192 ; pub const EXTI14 : u32 = 16384 ; pub const EXTI15 : u32 = 32768 ; pub const EXTI16 : u32 = 65536 ; pub const EXTI17 : u32 = 131072 ; pub const EXTI18 : u32 = 262144 ; pub const EXTI19 : u32 = 524288 ; pub const EXTI20 : u32 = 1048576 ; pub const EXTI21 : u32 = 2097152 ; pub const EXTI22 : u32 = 4194304 ; pub const EXTI23 : u32 = 8388608 ; pub const EXTI24 : u32 = 16777216 ; pub const EXTI25 : u32 = 33554432 ; pub const EXTI26 : u32 = 67108864 ; pub const EXTI27 : u32 = 134217728 ; pub const EXTI28 : u32 = 268435456 ; pub const EXTI29 : u32 = 536870912 ; pub const EXTI30 : u32 = 1073741824 ; pub const EXTI31 : u32 = 2147483648 ; pub const EXTI32 : u32 = 1 ; pub const EXTI33 : u32 = 2 ; pub const EXTI34 : u32 = 4 ; pub const EXTI35 : u32 = 8 ; pub const EXTI36 : u32 = 16 ; pub const EXTI37 : u32 = 32 ; pub const FLASH_ACR_LATENCY_SHIFT : u32 = 0 ; pub const FLASH_ACR_LATENCY : u32 = 7 ; pub const FLASH_ACR_PRFTBS : u32 = 32 ; pub const FLASH_ACR_PRFTBE : u32 = 16 ; pub const FLASH_SR_EOP : u32 = 32 ; pub const FLASH_SR_WRPRTERR : u32 = 16 ; pub const FLASH_SR_PGERR : u32 = 4 ; pub const FLASH_SR_BSY : u32 = 1 ; pub const FLASH_CR_EOPIE : u32 = 4096 ; pub const FLASH_CR_ERRIE : u32 = 1024 ; pub const FLASH_CR_OPTWRE : u32 = 512 ; pub const FLASH_CR_LOCK : u32 = 128 ; pub const FLASH_CR_STRT : u32 = 64 ; pub const FLASH_CR_OPTER : u32 = 32 ; pub const FLASH_CR_OPTPG : u32 = 16 ; pub const FLASH_CR_MER : u32 = 4 ; pub const FLASH_CR_PER : u32 = 2 ; pub const FLASH_CR_PG : u32 = 1 ; pub const FLASH_OBR_RDPRT_SHIFT : u32 = 1 ; pub const FLASH_OBR_OPTERR : u32 = 1 ; pub const FLASH_ACR_LATENCY_0WS : u32 = 0 ; pub const FLASH_ACR_LATENCY_1WS : u32 = 1 ; pub const FLASH_ACR_LATENCY_2WS : u32 = 2 ; pub const FLASH_ACR_HLFCYA : u32 = 8 ; pub const FLASH_OBR_NRST_STDBY : u32 = 16 ; pub const FLASH_OBR_NRST_STOP : u32 = 8 ; pub const FLASH_OBR_WDG_SW : u32 = 4 ; pub const FLASH_OBR_RDPRT_EN : u32 = 2 ; pub const FSMC_BANK1_BASE : u32 = 1610612736 ; pub const FSMC_BANK2_BASE : u32 = 1879048192 ; pub const FSMC_BANK3_BASE : u32 = 2147483648 ; pub const FSMC_BANK4_BASE : u32 = 2415919104 ; pub const FSMC_BCR_CBURSTRW : u32 = 524288 ; pub const FSMC_BCR_ASYNCWAIT : u32 = 32768 ; pub const FSMC_BCR_EXTMOD : u32 = 16384 ; pub const FSMC_BCR_WAITEN : u32 = 8192 ; pub const FSMC_BCR_WREN : u32 = 4096 ; pub const FSMC_BCR_WAITCFG : u32 = 2048 ; pub const FSMC_BCR_WRAPMOD : u32 = 1024 ; pub const FSMC_BCR_WAITPOL : u32 = 512 ; pub const FSMC_BCR_BURSTEN : u32 = 256 ; pub const FSMC_BCR_FACCEN : u32 = 64 ; pub const FSMC_BCR_MWID : u32 = 16 ; pub const FSMC_BCR_MTYP : u32 = 4 ; pub const FSMC_BCR_MUXEN : u32 = 2 ; pub const FSMC_BCR_MBKEN : u32 = 1 ; pub const FSMC_BTx_ACCMOD_A : u32 = 0 ; pub const FSMC_BTx_ACCMOD_B : u32 = 1 ; pub const FSMC_BTx_ACCMOD_C : u32 = 2 ; pub const FSMC_BTx_ACCMOD_D : u32 = 3 ; pub const FSMC_BTR_ACCMOD : u32 = 268435456 ; pub const FSMC_BTR_DATLAT : u32 = 16777216 ; pub const FSMC_BTR_CLKDIV : u32 = 1048576 ; pub const FSMC_BTR_BUSTURN : u32 = 65536 ; pub const FSMC_BTR_DATAST : u32 = 256 ; pub const FSMC_BTR_ADDHLD : u32 = 16 ; pub const FSMC_BTR_ADDSET : u32 = 1 ; pub const FSMC_BWTR_ACCMOD : u32 = 268435456 ; pub const FSMC_BWTR_DATLAT : u32 = 16777216 ; pub const FSMC_BWTR_CLKDIV : u32 = 1048576 ; pub const FSMC_BWTR_DATAST : u32 = 256 ; pub const FSMC_BWTR_ADDHLD : u32 = 16 ; pub const FSMC_BWTR_ADDSET : u32 = 1 ; pub const FSMC_PCR_ECCPS : u32 = 131072 ; pub const FSMC_PCR_TAR : u32 = 8192 ; pub const FSMC_PCR_TCLR : u32 = 512 ; pub const FSMC_PCR_ECCEN : u32 = 64 ; pub const FSMC_PCR_PWID : u32 = 16 ; pub const FSMC_PCR_PTYP : u32 = 8 ; pub const FSMC_PCR_PBKEN : u32 = 4 ; pub const FSMC_PCR_PWAITEN : u32 = 2 ; pub const FSMC_SR_FEMPT : u32 = 64 ; pub const FSMC_SR_IFEN : u32 = 32 ; pub const FSMC_SR_ILEN : u32 = 16 ; pub const FSMC_SR_IREN : u32 = 8 ; pub const FSMC_SR_IFS : u32 = 4 ; pub const FSMC_SR_ILS : u32 = 2 ; pub const FSMC_SR_IRS : u32 = 1 ; pub const FSMC_PMEM_MEMHIZX : u32 = 16777216 ; pub const FSMC_PMEM_MEMHOLDX : u32 = 65536 ; pub const FSMC_PMEM_MEMWAITX : u32 = 256 ; pub const FSMC_PMEM_MEMSETX : u32 = 1 ; pub const FSMC_PATT_ATTHIZX : u32 = 16777216 ; pub const FSMC_PATT_ATTHOLDX : u32 = 65536 ; pub const FSMC_PATT_ATTWAITX : u32 = 256 ; pub const FSMC_PATT_ATTSETX : u32 = 1 ; pub const FSMC_PIO4_IOHIZX : u32 = 16777216 ; pub const FSMC_PIO4_IOHOLDX : u32 = 65536 ; pub const FSMC_PIO4_IOWAITX : u32 = 256 ; pub const FSMC_PIO4_IOSETX : u32 = 1 ; pub const FSMC_ECCR_ECCX : u32 = 1 ; pub const GPIO_LCKK : u32 = 65536 ; pub const GPIO0 : u32 = 1 ; pub const GPIO1 : u32 = 2 ; pub const GPIO2 : u32 = 4 ; pub const GPIO3 : u32 = 8 ; pub const GPIO4 : u32 = 16 ; pub const GPIO5 : u32 = 32 ; pub const GPIO6 : u32 = 64 ; pub const GPIO7 : u32 = 128 ; pub const GPIO8 : u32 = 256 ; pub const GPIO9 : u32 = 512 ; pub const GPIO10 : u32 = 1024 ; pub const GPIO11 : u32 = 2048 ; pub const GPIO12 : u32 = 4096 ; pub const GPIO13 : u32 = 8192 ; pub const GPIO14 : u32 = 16384 ; pub const GPIO15 : u32 = 32768 ; pub const GPIO_ALL : u32 = 65535 ; pub const GPIOA : u32 = 1073809408 ; pub const GPIOB : u32 = 1073810432 ; pub const GPIOC : u32 = 1073811456 ; pub const GPIOD : u32 = 1073812480 ; pub const GPIOE : u32 = 1073813504 ; pub const GPIOF : u32 = 1073814528 ; pub const GPIOG : u32 = 1073815552 ; pub const GPIO_CAN1_RX : u32 = 2048 ; pub const GPIO_CAN1_TX : u32 = 4096 ; pub const GPIO_CAN_RX : u32 = 2048 ; pub const GPIO_CAN_TX : u32 = 4096 ; pub const GPIO_CAN_PB_RX : u32 = 256 ; pub const GPIO_CAN_PB_TX : u32 = 512 ; pub const GPIO_CAN1_PB_RX : u32 = 256 ; pub const GPIO_CAN1_PB_TX : u32 = 512 ; pub const GPIO_CAN_PD_RX : u32 = 1 ; pub const GPIO_CAN_PD_TX : u32 = 2 ; pub const GPIO_CAN1_PD_RX : u32 = 1 ; pub const GPIO_CAN1_PD_TX : u32 = 2 ; pub const GPIO_BANK_CAN1_RX : u32 = 1073809408 ; pub const GPIO_BANK_CAN1_TX : u32 = 1073809408 ; pub const GPIO_BANK_CAN_RX : u32 = 1073809408 ; pub const GPIO_BANK_CAN_TX : u32 = 1073809408 ; pub const GPIO_BANK_CAN_PB_RX : u32 = 1073810432 ; pub const GPIO_BANK_CAN_PB_TX : u32 = 1073810432 ; pub const GPIO_BANK_CAN1_PB_RX : u32 = 1073810432 ; pub const GPIO_BANK_CAN1_PB_TX : u32 = 1073810432 ; pub const GPIO_BANK_CAN_PD_RX : u32 = 1073812480 ; pub const GPIO_BANK_CAN_PD_TX : u32 = 1073812480 ; pub const GPIO_BANK_CAN1_PD_RX : u32 = 1073812480 ; pub const GPIO_BANK_CAN1_PD_TX : u32 = 1073812480 ; pub const GPIO_CAN2_RX : u32 = 4096 ; pub const GPIO_CAN2_TX : u32 = 8192 ; pub const GPIO_CAN2_RE_RX : u32 = 32 ; pub const GPIO_CAN2_RE_TX : u32 = 64 ; pub const GPIO_BANK_CAN2_RX : u32 = 1073810432 ; pub const GPIO_BANK_CAN2_TX : u32 = 1073810432 ; pub const GPIO_BANK_CAN2_RE_RX : u32 = 1073810432 ; pub const GPIO_BANK_CAN2_RE_TX : u32 = 1073810432 ; pub const GPIO_JTMS_SWDIO : u32 = 8192 ; pub const GPIO_JTCK_SWCLK : u32 = 16384 ; pub const GPIO_JTDI : u32 = 32768 ; pub const GPIO_JTDO_TRACESWO : u32 = 8 ; pub const GPIO_JNTRST : u32 = 16 ; pub const GPIO_TRACECK : u32 = 4 ; pub const GPIO_TRACED0 : u32 = 8 ; pub const GPIO_TRACED1 : u32 = 16 ; pub const GPIO_TRACED2 : u32 = 32 ; pub const GPIO_TRACED3 : u32 = 64 ; pub const GPIO_BANK_JTMS_SWDIO : u32 = 1073809408 ; pub const GPIO_BANK_JTCK_SWCLK : u32 = 1073809408 ; pub const GPIO_BANK_JTDI : u32 = 1073809408 ; pub const GPIO_BANK_JTDO_TRACESWO : u32 = 1073810432 ; pub const GPIO_BANK_JNTRST : u32 = 1073810432 ; pub const GPIO_BANK_TRACECK : u32 = 1073813504 ; pub const GPIO_BANK_TRACED0 : u32 = 1073813504 ; pub const GPIO_BANK_TRACED1 : u32 = 1073813504 ; pub const GPIO_BANK_TRACED2 : u32 = 1073813504 ; pub const GPIO_BANK_TRACED3 : u32 = 1073813504 ; pub const GPIO_TIM5_CH1 : u32 = 1 ; pub const GPIO_TIM5_CH2 : u32 = 2 ; pub const GPIO_TIM5_CH3 : u32 = 4 ; pub const GPIO_TIM5_CH4 : u32 = 8 ; pub const GPIO_BANK_TIM5_CH1 : u32 = 1073809408 ; pub const GPIO_BANK_TIM5_CH2 : u32 = 1073809408 ; pub const GPIO_BANK_TIM5_CH3 : u32 = 1073809408 ; pub const GPIO_BANK_TIM5_CH4 : u32 = 1073809408 ; pub const GPIO_BANK_TIM5 : u32 = 1073809408 ; pub const GPIO_TIM4_CH1 : u32 = 64 ; pub const GPIO_TIM4_CH2 : u32 = 128 ; pub const GPIO_TIM4_CH3 : u32 = 256 ; pub const GPIO_TIM4_CH4 : u32 = 512 ; pub const GPIO_TIM4_RE_CH1 : u32 = 4096 ; pub const GPIO_TIM4_RE_CH2 : u32 = 8192 ; pub const GPIO_TIM4_RE_CH3 : u32 = 16384 ; pub const GPIO_TIM4_RE_CH4 : u32 = 32768 ; pub const GPIO_BANK_TIM4_CH1 : u32 = 1073810432 ; pub const GPIO_BANK_TIM4_CH2 : u32 = 1073810432 ; pub const GPIO_BANK_TIM4_CH3 : u32 = 1073810432 ; pub const GPIO_BANK_TIM4_CH4 : u32 = 1073810432 ; pub const GPIO_BANK_TIM4 : u32 = 1073810432 ; pub const GPIO_BANK_TIM4_RE_CH1 : u32 = 1073812480 ; pub const GPIO_BANK_TIM4_RE_CH2 : u32 = 1073812480 ; pub const GPIO_BANK_TIM4_RE_CH3 : u32 = 1073812480 ; pub const GPIO_BANK_TIM4_RE_CH4 : u32 = 1073812480 ; pub const GPIO_BANK_TIM4_RE : u32 = 1073812480 ; pub const GPIO_TIM3_CH1 : u32 = 64 ; pub const GPIO_TIM3_CH2 : u32 = 128 ; pub const GPIO_TIM3_CH3 : u32 = 1 ; pub const GPIO_TIM3_CH4 : u32 = 2 ; pub const GPIO_TIM3_PR_CH1 : u32 = 16 ; pub const GPIO_TIM3_PR_CH2 : u32 = 32 ; pub const GPIO_TIM3_PR_CH3 : u32 = 1 ; pub const GPIO_TIM3_PR_CH4 : u32 = 2 ; pub const GPIO_TIM3_FR_CH1 : u32 = 64 ; pub const GPIO_TIM3_FR_CH2 : u32 = 128 ; pub const GPIO_TIM3_FR_CH3 : u32 = 256 ; pub const GPIO_TIM3_FR_CH4 : u32 = 512 ; pub const GPIO_BANK_TIM3_CH1 : u32 = 1073809408 ; pub const GPIO_BANK_TIM3_CH2 : u32 = 1073809408 ; pub const GPIO_BANK_TIM3_CH3 : u32 = 1073810432 ; pub const GPIO_BANK_TIM3_CH4 : u32 = 1073810432 ; pub const GPIO_BANK_TIM3_CH12 : u32 = 1073809408 ; pub const GPIO_BANK_TIM3_CH34 : u32 = 1073810432 ; pub const GPIO_BANK_TIM3_PR_CH1 : u32 = 1073810432 ; pub const GPIO_BANK_TIM3_PR_CH2 : u32 = 1073810432 ; pub const GPIO_BANK_TIM3_PR_CH3 : u32 = 1073810432 ; pub const GPIO_BANK_TIM3_PR_CH4 : u32 = 1073810432 ; pub const GPIO_BANK_TIM3_PR : u32 = 1073810432 ; pub const GPIO_BANK_TIM3_FR_CH1 : u32 = 1073811456 ; pub const GPIO_BANK_TIM3_FR_CH2 : u32 = 1073811456 ; pub const GPIO_BANK_TIM3_FR_CH3 : u32 = 1073811456 ; pub const GPIO_BANK_TIM3_FR_CH4 : u32 = 1073811456 ; pub const GPIO_BANK_TIM3_FR : u32 = 1073811456 ; pub const GPIO_TIM2_CH1_ETR : u32 = 1 ; pub const GPIO_TIM2_CH2 : u32 = 2 ; pub const GPIO_TIM2_CH3 : u32 = 4 ; pub const GPIO_TIM2_CH4 : u32 = 8 ; pub const GPIO_TIM2_PR1_CH1_ETR : u32 = 32768 ; pub const GPIO_TIM2_PR1_CH2 : u32 = 8 ; pub const GPIO_TIM2_PR1_CH3 : u32 = 4 ; pub const GPIO_TIM2_PR1_CH4 : u32 = 8 ; pub const GPIO_TIM2_PR2_CH1_ETR : u32 = 1 ; pub const GPIO_TIM2_PR2_CH2 : u32 = 2 ; pub const GPIO_TIM2_PR2_CH3 : u32 = 1024 ; pub const GPIO_TIM2_PR2_CH4 : u32 = 2048 ; pub const GPIO_TIM2_FR_CH1_ETR : u32 = 32768 ; pub const GPIO_TIM2_FR_CH2 : u32 = 8 ; pub const GPIO_TIM2_FR_CH3 : u32 = 1024 ; pub const GPIO_TIM2_FR_CH4 : u32 = 2048 ; pub const GPIO_BANK_TIM2_CH1_ETR : u32 = 1073809408 ; pub const GPIO_BANK_TIM2_CH2 : u32 = 1073809408 ; pub const GPIO_BANK_TIM2_CH3 : u32 = 1073809408 ; pub const GPIO_BANK_TIM2_CH4 : u32 = 1073809408 ; pub const GPIO_BANK_TIM2 : u32 = 1073809408 ; pub const GPIO_BANK_TIM2_PR1_CH1_ETR : u32 = 1073809408 ; pub const GPIO_BANK_TIM2_PR1_CH2 : u32 = 1073810432 ; pub const GPIO_BANK_TIM2_PR1_CH3 : u32 = 1073809408 ; pub const GPIO_BANK_TIM2_PR1_CH4 : u32 = 1073809408 ; pub const GPIO_BANK_TIM2_PR1_CH134 : u32 = 1073809408 ; pub const GPIO_BANK_TIM2_PR2_CH1_ETR : u32 = 1073809408 ; pub const GPIO_BANK_TIM2_PR2_CH2 : u32 = 1073809408 ; pub const GPIO_BANK_TIM2_PR2_CH3 : u32 = 1073810432 ; pub const GPIO_BANK_TIM2_PR2_CH4 : u32 = 1073810432 ; pub const GPIO_BANK_TIM2_PR2_CH12 : u32 = 1073809408 ; pub const GPIO_BANK_TIM2_PR2_CH34 : u32 = 1073810432 ; pub const GPIO_BANK_TIM2_FR_CH1_ETR : u32 = 1073809408 ; pub const GPIO_BANK_TIM2_FR_CH2 : u32 = 1073810432 ; pub const GPIO_BANK_TIM2_FR_CH3 : u32 = 1073810432 ; pub const GPIO_BANK_TIM2_FR_CH4 : u32 = 1073810432 ; pub const GPIO_BANK_TIM2_FR_CH234 : u32 = 1073810432 ; pub const GPIO_TIM1_ETR : u32 = 4096 ; pub const GPIO_TIM1_CH1 : u32 = 256 ; pub const GPIO_TIM1_CH2 : u32 = 512 ; pub const GPIO_TIM1_CH3 : u32 = 1024 ; pub const GPIO_TIM1_CH4 : u32 = 2048 ; pub const GPIO_TIM1_BKIN : u32 = 4096 ; pub const GPIO_TIM1_CH1N : u32 = 8192 ; pub const GPIO_TIM1_CH2N : u32 = 16384 ; pub const GPIO_TIM1_CH3N : u32 = 32768 ; pub const GPIO_TIM1_PR_ETR : u32 = 4096 ; pub const GPIO_TIM1_PR_CH1 : u32 = 256 ; pub const GPIO_TIM1_PR_CH2 : u32 = 512 ; pub const GPIO_TIM1_PR_CH3 : u32 = 1024 ; pub const GPIO_TIM1_PR_CH4 : u32 = 2048 ; pub const GPIO_TIM1_PR_BKIN : u32 = 64 ; pub const GPIO_TIM1_PR_CH1N : u32 = 128 ; pub const GPIO_TIM1_PR_CH2N : u32 = 1 ; pub const GPIO_TIM1_PR_CH3N : u32 = 2 ; pub const GPIO_TIM1_FR_ETR : u32 = 128 ; pub const GPIO_TIM1_FR_CH1 : u32 = 512 ; pub const GPIO_TIM1_FR_CH2 : u32 = 2048 ; pub const GPIO_TIM1_FR_CH3 : u32 = 8192 ; pub const GPIO_TIM1_FR_CH4 : u32 = 16384 ; pub const GPIO_TIM1_FR_BKIN : u32 = 32768 ; pub const GPIO_TIM1_FR_CH1N : u32 = 256 ; pub const GPIO_TIM1_FR_CH2N : u32 = 1024 ; pub const GPIO_TIM1_FR_CH3N : u32 = 4096 ; pub const GPIO_BANK_TIM1_ETR : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_CH1 : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_CH2 : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_CH3 : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_CH4 : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_BKIN : u32 = 1073810432 ; pub const GPIO_BANK_TIM1_CH1N : u32 = 1073810432 ; pub const GPIO_BANK_TIM1_CH2N : u32 = 1073810432 ; pub const GPIO_BANK_TIM1_CH3N : u32 = 1073810432 ; pub const GPIO_BANK_TIM1_ETR_CH1234 : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_BKIN_CH123N : u32 = 1073810432 ; pub const GPIO_BANK_TIM1_PR_ETR : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_PR_CH1 : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_PR_CH2 : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_PR_CH3 : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_PR_CH4 : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_PR_BKIN : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_PR_CH1N : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_PR_CH2N : u32 = 1073810432 ; pub const GPIO_BANK_TIM1_PR_CH3N : u32 = 1073810432 ; pub const GPIO_BANK_TIM1_PR_ETR_CH1234_BKIN_CH1N : u32 = 1073809408 ; pub const GPIO_BANK_TIM1_PR_CH23N : u32 = 1073810432 ; pub const GPIO_BANK_TIM1_FR_ETR : u32 = 1073813504 ; pub const GPIO_BANK_TIM1_FR_CH1 : u32 = 1073813504 ; pub const GPIO_BANK_TIM1_FR_CH2 : u32 = 1073813504 ; pub const GPIO_BANK_TIM1_FR_CH3 : u32 = 1073813504 ; pub const GPIO_BANK_TIM1_FR_CH4 : u32 = 1073813504 ; pub const GPIO_BANK_TIM1_FR_BKIN : u32 = 1073813504 ; pub const GPIO_BANK_TIM1_FR_CH1N : u32 = 1073813504 ; pub const GPIO_BANK_TIM1_FR_CH2N : u32 = 1073813504 ; pub const GPIO_BANK_TIM1_FR_CH3N : u32 = 1073813504 ; pub const GPIO_BANK_TIM1_FR : u32 = 1073813504 ; pub const GPIO_UART5_TX : u32 = 4096 ; pub const GPIO_UART5_RX : u32 = 4 ; pub const GPIO_BANK_UART5_TX : u32 = 1073811456 ; pub const GPIO_BANK_UART5_RX : u32 = 1073812480 ; pub const GPIO_UART4_TX : u32 = 1024 ; pub const GPIO_UART4_RX : u32 = 2048 ; pub const GPIO_BANK_UART4_TX : u32 = 1073811456 ; pub const GPIO_BANK_UART4_RX : u32 = 1073811456 ; pub const GPIO_USART3_TX : u32 = 1024 ; pub const GPIO_USART3_RX : u32 = 2048 ; pub const GPIO_USART3_CK : u32 = 4096 ; pub const GPIO_USART3_CTS : u32 = 8192 ; pub const GPIO_USART3_RTS : u32 = 16384 ; pub const GPIO_USART3_PR_TX : u32 = 1024 ; pub const GPIO_USART3_PR_RX : u32 = 2048 ; pub const GPIO_USART3_PR_CK : u32 = 4096 ; pub const GPIO_USART3_PR_CTS : u32 = 8192 ; pub const GPIO_USART3_PR_RTS : u32 = 16384 ; pub const GPIO_USART3_FR_TX : u32 = 256 ; pub const GPIO_USART3_FR_RX : u32 = 512 ; pub const GPIO_USART3_FR_CK : u32 = 1024 ; pub const GPIO_USART3_FR_CTS : u32 = 2048 ; pub const GPIO_USART3_FR_RTS : u32 = 4096 ; pub const GPIO_BANK_USART3_TX : u32 = 1073810432 ; pub const GPIO_BANK_USART3_RX : u32 = 1073810432 ; pub const GPIO_BANK_USART3_CK : u32 = 1073810432 ; pub const GPIO_BANK_USART3_CTS : u32 = 1073810432 ; pub const GPIO_BANK_USART3_RTS : u32 = 1073810432 ; pub const GPIO_BANK_USART3_PR_TX : u32 = 1073811456 ; pub const GPIO_BANK_USART3_PR_RX : u32 = 1073811456 ; pub const GPIO_BANK_USART3_PR_CK : u32 = 1073811456 ; pub const GPIO_BANK_USART3_PR_CTS : u32 = 1073810432 ; pub const GPIO_BANK_USART3_PR_RTS : u32 = 1073810432 ; pub const GPIO_BANK_USART3_FR_TX : u32 = 1073812480 ; pub const GPIO_BANK_USART3_FR_RX : u32 = 1073812480 ; pub const GPIO_BANK_USART3_FR_CK : u32 = 1073812480 ; pub const GPIO_BANK_USART3_FR_CTS : u32 = 1073812480 ; pub const GPIO_BANK_USART3_FR_RTS : u32 = 1073812480 ; pub const GPIO_USART2_CTS : u32 = 1 ; pub const GPIO_USART2_RTS : u32 = 2 ; pub const GPIO_USART2_TX : u32 = 4 ; pub const GPIO_USART2_RX : u32 = 8 ; pub const GPIO_USART2_CK : u32 = 16 ; pub const GPIO_USART2_RE_CTS : u32 = 8 ; pub const GPIO_USART2_RE_RTS : u32 = 16 ; pub const GPIO_USART2_RE_TX : u32 = 32 ; pub const GPIO_USART2_RE_RX : u32 = 64 ; pub const GPIO_USART2_RE_CK : u32 = 128 ; pub const GPIO_BANK_USART2_CTS : u32 = 1073809408 ; pub const GPIO_BANK_USART2_RTS : u32 = 1073809408 ; pub const GPIO_BANK_USART2_TX : u32 = 1073809408 ; pub const GPIO_BANK_USART2_RX : u32 = 1073809408 ; pub const GPIO_BANK_USART2_CK : u32 = 1073809408 ; pub const GPIO_BANK_USART2_RE_CTS : u32 = 1073812480 ; pub const GPIO_BANK_USART2_RE_RTS : u32 = 1073812480 ; pub const GPIO_BANK_USART2_RE_TX : u32 = 1073812480 ; pub const GPIO_BANK_USART2_RE_RX : u32 = 1073812480 ; pub const GPIO_BANK_USART2_RE_CK : u32 = 1073812480 ; pub const GPIO_USART1_TX : u32 = 512 ; pub const GPIO_USART1_RX : u32 = 1024 ; pub const GPIO_USART1_RE_TX : u32 = 64 ; pub const GPIO_USART1_RE_RX : u32 = 128 ; pub const GPIO_BANK_USART1_TX : u32 = 1073809408 ; pub const GPIO_BANK_USART1_RX : u32 = 1073809408 ; pub const GPIO_BANK_USART1_RE_TX : u32 = 1073810432 ; pub const GPIO_BANK_USART1_RE_RX : u32 = 1073810432 ; pub const GPIO_I2C1_SMBAI : u32 = 32 ; pub const GPIO_I2C1_SCL : u32 = 64 ; pub const GPIO_I2C1_SDA : u32 = 128 ; pub const GPIO_I2C1_RE_SMBAI : u32 = 32 ; pub const GPIO_I2C1_RE_SCL : u32 = 256 ; pub const GPIO_I2C1_RE_SDA : u32 = 512 ; pub const GPIO_BANK_I2C1_SMBAI : u32 = 1073810432 ; pub const GPIO_BANK_I2C1_SCL : u32 = 1073810432 ; pub const GPIO_BANK_I2C1_SDA : u32 = 1073810432 ; pub const GPIO_BANK_I2C1_RE_SMBAI : u32 = 1073810432 ; pub const GPIO_BANK_I2C1_RE_SCL : u32 = 1073810432 ; pub const GPIO_BANK_I2C1_RE_SDA : u32 = 1073810432 ; pub const GPIO_I2C2_SCL : u32 = 1024 ; pub const GPIO_I2C2_SDA : u32 = 2048 ; pub const GPIO_I2C2_SMBAI : u32 = 4096 ; pub const GPIO_BANK_I2C2_SCL : u32 = 1073810432 ; pub const GPIO_BANK_I2C2_SDA : u32 = 1073810432 ; pub const GPIO_BANK_I2C2_SMBAI : u32 = 1073810432 ; pub const GPIO_SPI1_NSS : u32 = 16 ; pub const GPIO_SPI1_SCK : u32 = 32 ; pub const GPIO_SPI1_MISO : u32 = 64 ; pub const GPIO_SPI1_MOSI : u32 = 128 ; pub const GPIO_SPI1_RE_NSS : u32 = 32768 ; pub const GPIO_SPI1_RE_SCK : u32 = 8 ; pub const GPIO_SPI1_RE_MISO : u32 = 16 ; pub const GPIO_SPI1_RE_MOSI : u32 = 32 ; pub const GPIO_BANK_SPI1_NSS : u32 = 1073809408 ; pub const GPIO_BANK_SPI1_SCK : u32 = 1073809408 ; pub const GPIO_BANK_SPI1_MISO : u32 = 1073809408 ; pub const GPIO_BANK_SPI1_MOSI : u32 = 1073809408 ; pub const GPIO_BANK_SPI1_RE_NSS : u32 = 1073809408 ; pub const GPIO_BANK_SPI1_RE_SCK : u32 = 1073810432 ; pub const GPIO_BANK_SPI1_RE_MISO : u32 = 1073810432 ; pub const GPIO_BANK_SPI1_RE_MOSI : u32 = 1073810432 ; pub const GPIO_SPI2_NSS : u32 = 4096 ; pub const GPIO_SPI2_SCK : u32 = 8192 ; pub const GPIO_SPI2_MISO : u32 = 16384 ; pub const GPIO_SPI2_MOSI : u32 = 32768 ; pub const GPIO_BANK_SPI2_NSS : u32 = 1073810432 ; pub const GPIO_BANK_SPI2_SCK : u32 = 1073810432 ; pub const GPIO_BANK_SPI2_MISO : u32 = 1073810432 ; pub const GPIO_BANK_SPI2_MOSI : u32 = 1073810432 ; pub const GPIO_SPI3_NSS : u32 = 32768 ; pub const GPIO_SPI3_SCK : u32 = 8 ; pub const GPIO_SPI3_MISO : u32 = 16 ; pub const GPIO_SPI3_MOSI : u32 = 32 ; pub const GPIO_SPI3_RE_NSS : u32 = 16 ; pub const GPIO_SPI3_RE_SCK : u32 = 1024 ; pub const GPIO_SPI3_RE_MISO : u32 = 2048 ; pub const GPIO_SPI3_RE_MOSI : u32 = 4096 ; pub const GPIO_BANK_SPI3_NSS : u32 = 1073809408 ; pub const GPIO_BANK_SPI3_SCK : u32 = 1073810432 ; pub const GPIO_BANK_SPI3_MISO : u32 = 1073810432 ; pub const GPIO_BANK_SPI3_MOSI : u32 = 1073810432 ; pub const GPIO_BANK_SPI3_RE_NSS : u32 = 1073809408 ; pub const GPIO_BANK_SPI3_RE_SCK : u32 = 1073811456 ; pub const GPIO_BANK_SPI3_RE_MISO : u32 = 1073811456 ; pub const GPIO_BANK_SPI3_RE_MOSI : u32 = 1073811456 ; pub const GPIO_ETH_RX_DV_CRS_DV : u32 = 128 ; pub const GPIO_ETH_RXD0 : u32 = 16 ; pub const GPIO_ETH_RXD1 : u32 = 32 ; pub const GPIO_ETH_RXD2 : u32 = 1 ; pub const GPIO_ETH_RXD3 : u32 = 2 ; pub const GPIO_ETH_RE_RX_DV_CRS_DV : u32 = 256 ; pub const GPIO_ETH_RE_RXD0 : u32 = 512 ; pub const GPIO_ETH_RE_RXD1 : u32 = 1024 ; pub const GPIO_ETH_RE_RXD2 : u32 = 2048 ; pub const GPIO_ETH_RE_RXD3 : u32 = 4096 ; pub const GPIO_BANK_ETH_RX_DV_CRS_DV : u32 = 1073809408 ; pub const GPIO_BANK_ETH_RXD0 : u32 = 1073811456 ; pub const GPIO_BANK_ETH_RXD1 : u32 = 1073811456 ; pub const GPIO_BANK_ETH_RXD2 : u32 = 1073810432 ; pub const GPIO_BANK_ETH_RXD3 : u32 = 1073810432 ; pub const GPIO_BANK_ETH_RE_RX_DV_CRS_DV : u32 = 1073812480 ; pub const GPIO_BANK_ETH_RE_RXD0 : u32 = 1073812480 ; pub const GPIO_BANK_ETH_RE_RXD1 : u32 = 1073812480 ; pub const GPIO_BANK_ETH_RE_RXD2 : u32 = 1073812480 ; pub const GPIO_BANK_ETH_RE_RXD3 : u32 = 1073812480 ; pub const GPIO_CNF_INPUT_ANALOG : u32 = 0 ; pub const GPIO_CNF_INPUT_FLOAT : u32 = 1 ; pub const GPIO_CNF_INPUT_PULL_UPDOWN : u32 = 2 ; pub const GPIO_CNF_OUTPUT_PUSHPULL : u32 = 0 ; pub const GPIO_CNF_OUTPUT_OPENDRAIN : u32 = 1 ; pub const GPIO_CNF_OUTPUT_ALTFN_PUSHPULL : u32 = 2 ; pub const GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN : u32 = 3 ; pub const GPIO_MODE_INPUT : u32 = 0 ; pub const GPIO_MODE_OUTPUT_10_MHZ : u32 = 1 ; pub const GPIO_MODE_OUTPUT_2_MHZ : u32 = 2 ; pub const GPIO_MODE_OUTPUT_50_MHZ : u32 = 3 ; pub const AFIO_EVCR_EVOE : u32 = 128 ; pub const AFIO_EVCR_PORT_PA : u32 = 0 ; pub const AFIO_EVCR_PORT_PB : u32 = 16 ; pub const AFIO_EVCR_PORT_PC : u32 = 32 ; pub const AFIO_EVCR_PORT_PD : u32 = 48 ; pub const AFIO_EVCR_PORT_PE : u32 = 64 ; pub const AFIO_EVCR_PIN_Px0 : u32 = 0 ; pub const AFIO_EVCR_PIN_Px1 : u32 = 1 ; pub const AFIO_EVCR_PIN_Px2 : u32 = 2 ; pub const AFIO_EVCR_PIN_Px3 : u32 = 3 ; pub const AFIO_EVCR_PIN_Px4 : u32 = 4 ; pub const AFIO_EVCR_PIN_Px5 : u32 = 5 ; pub const AFIO_EVCR_PIN_Px6 : u32 = 6 ; pub const AFIO_EVCR_PIN_Px7 : u32 = 7 ; pub const AFIO_EVCR_PIN_Px8 : u32 = 8 ; pub const AFIO_EVCR_PIN_Px9 : u32 = 9 ; pub const AFIO_EVCR_PIN_Px10 : u32 = 10 ; pub const AFIO_EVCR_PIN_Px11 : u32 = 11 ; pub const AFIO_EVCR_PIN_Px12 : u32 = 12 ; pub const AFIO_EVCR_PIN_Px13 : u32 = 13 ; pub const AFIO_EVCR_PIN_Px14 : u32 = 14 ; pub const AFIO_EVCR_PIN_Px15 : u32 = 15 ; pub const AFIO_MAPR_PTP_PPS_REMAP : u32 = 1073741824 ; pub const AFIO_MAPR_TIM2ITR1_IREMAP : u32 = 536870912 ; pub const AFIO_MAPR_SPI3_REMAP : u32 = 268435456 ; pub const AFIO_MAPR_MII_RMII_SEL : u32 = 8388608 ; pub const AFIO_MAPR_CAN2_REMAP : u32 = 4194304 ; pub const AFIO_MAPR_ETH_REMAP : u32 = 2097152 ; pub const AFIO_MAPR_SWJ_MASK : u32 = 117440512 ; pub const AFIO_MAPR_SWJ_CFG_FULL_SWJ : u32 = 0 ; pub const AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST : u32 = 16777216 ; pub const AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON : u32 = 33554432 ; pub const AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF : u32 = 67108864 ; pub const AFIO_MAPR_ADC2_ETRGREG_REMAP : u32 = 1048576 ; pub const AFIO_MAPR_ADC2_ETRGINJ_REMAP : u32 = 524288 ; pub const AFIO_MAPR_ADC1_ETRGREG_REMAP : u32 = 262144 ; pub const AFIO_MAPR_ADC1_ETRGINJ_REMAP : u32 = 131072 ; pub const AFIO_MAPR_TIM5CH4_IREMAP : u32 = 65536 ; pub const AFIO_MAPR_PD01_REMAP : u32 = 32768 ; pub const AFIO_MAPR_TIM4_REMAP : u32 = 4096 ; pub const AFIO_MAPR_USART2_REMAP : u32 = 8 ; pub const AFIO_MAPR_USART1_REMAP : u32 = 4 ; pub const AFIO_MAPR_I2C1_REMAP : u32 = 2 ; pub const AFIO_MAPR_SPI1_REMAP : u32 = 1 ; pub const AFIO_MAPR_CAN1_REMAP_PORTA : u32 = 0 ; pub const AFIO_MAPR_CAN1_REMAP_PORTB : u32 = 16384 ; pub const AFIO_MAPR_CAN1_REMAP_PORTD : u32 = 24576 ; pub const AFIO_MAPR_TIM3_REMAP_NO_REMAP : u32 = 0 ; pub const AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP : u32 = 2048 ; pub const AFIO_MAPR_TIM3_REMAP_FULL_REMAP : u32 = 3072 ; pub const AFIO_MAPR_TIM2_REMAP_NO_REMAP : u32 = 0 ; pub const AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 : u32 = 256 ; pub const AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 : u32 = 512 ; pub const AFIO_MAPR_TIM2_REMAP_FULL_REMAP : u32 = 768 ; pub const AFIO_MAPR_TIM1_REMAP_NO_REMAP : u32 = 0 ; pub const AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP : u32 = 64 ; pub const AFIO_MAPR_TIM1_REMAP_FULL_REMAP : u32 = 192 ; pub const AFIO_MAPR_USART3_REMAP_NO_REMAP : u32 = 0 ; pub const AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP : u32 = 16 ; pub const AFIO_MAPR_USART3_REMAP_FULL_REMAP : u32 = 48 ; pub const AFIO_MAPR2_MISC_REMAP : u32 = 8192 ; pub const AFIO_MAPR2_TIM12_REMAP : u32 = 4096 ; pub const AFIO_MAPR2_TIM76_DAC_DMA_REMAPE : u32 = 2048 ; pub const AFIO_MAPR2_FSMC_NADV_DISCONNECT : u32 = 1024 ; pub const AFIO_MAPR2_TIM14_REMAP : u32 = 512 ; pub const AFIO_MAPR2_TIM13_REMAP : u32 = 256 ; pub const AFIO_MAPR2_TIM11_REMAP : u32 = 128 ; pub const AFIO_MAPR2_TIM10_REMAP : u32 = 64 ; pub const AFIO_MAPR2_TIM9_REMAP : u32 = 32 ; pub const AFIO_MAPR2_TIM1_DMA_REMAP : u32 = 16 ; pub const AFIO_MAPR2_CEC_REMAP : u32 = 8 ; pub const AFIO_MAPR2_TIM17_REMAP : u32 = 4 ; pub const AFIO_MAPR2_TIM16_REMAP : u32 = 2 ; pub const AFIO_MAPR1_TIM16_REMAP : u32 = 1 ; pub const AFIO_EXTI0 : u32 = 0 ; pub const AFIO_EXTI1 : u32 = 1 ; pub const AFIO_EXTI2 : u32 = 2 ; pub const AFIO_EXTI3 : u32 = 3 ; pub const AFIO_EXTI4 : u32 = 4 ; pub const AFIO_EXTI5 : u32 = 5 ; pub const AFIO_EXTI6 : u32 = 6 ; pub const AFIO_EXTI7 : u32 = 7 ; pub const AFIO_EXTI8 : u32 = 8 ; pub const AFIO_EXTI9 : u32 = 9 ; pub const AFIO_EXTI10 : u32 = 10 ; pub const AFIO_EXTI11 : u32 = 11 ; pub const AFIO_EXTI12 : u32 = 12 ; pub const AFIO_EXTI13 : u32 = 13 ; pub const AFIO_EXTI14 : u32 = 14 ; pub const AFIO_EXTI15 : u32 = 15 ; pub const I2C1 : u32 = 1073763328 ; pub const I2C2 : u32 = 1073764352 ; pub const I2C_CR1_SWRST : u32 = 32768 ; pub const I2C_CR1_ALERT : u32 = 8192 ; pub const I2C_CR1_PEC : u32 = 4096 ; pub const I2C_CR1_POS : u32 = 2048 ; pub const I2C_CR1_ACK : u32 = 1024 ; pub const I2C_CR1_STOP : u32 = 512 ; pub const I2C_CR1_START : u32 = 256 ; pub const I2C_CR1_NOSTRETCH : u32 = 128 ; pub const I2C_CR1_ENGC : u32 = 64 ; pub const I2C_CR1_ENPEC : u32 = 32 ; pub const I2C_CR1_ENARP : u32 = 16 ; pub const I2C_CR1_SMBTYPE : u32 = 8 ; pub const I2C_CR1_SMBUS : u32 = 2 ; pub const I2C_CR1_PE : u32 = 1 ; pub const I2C_CR2_LAST : u32 = 4096 ; pub const I2C_CR2_DMAEN : u32 = 2048 ; pub const I2C_CR2_ITBUFEN : u32 = 1024 ; pub const I2C_CR2_ITEVTEN : u32 = 512 ; pub const I2C_CR2_ITERREN : u32 = 256 ; pub const I2C_CR2_FREQ_2MHZ : u32 = 2 ; pub const I2C_CR2_FREQ_3MHZ : u32 = 3 ; pub const I2C_CR2_FREQ_4MHZ : u32 = 4 ; pub const I2C_CR2_FREQ_5MHZ : u32 = 5 ; pub const I2C_CR2_FREQ_6MHZ : u32 = 6 ; pub const I2C_CR2_FREQ_7MHZ : u32 = 7 ; pub const I2C_CR2_FREQ_8MHZ : u32 = 8 ; pub const I2C_CR2_FREQ_9MHZ : u32 = 9 ; pub const I2C_CR2_FREQ_10MHZ : u32 = 10 ; pub const I2C_CR2_FREQ_11MHZ : u32 = 11 ; pub const I2C_CR2_FREQ_12MHZ : u32 = 12 ; pub const I2C_CR2_FREQ_13MHZ : u32 = 13 ; pub const I2C_CR2_FREQ_14MHZ : u32 = 14 ; pub const I2C_CR2_FREQ_15MHZ : u32 = 15 ; pub const I2C_CR2_FREQ_16MHZ : u32 = 16 ; pub const I2C_CR2_FREQ_17MHZ : u32 = 17 ; pub const I2C_CR2_FREQ_18MHZ : u32 = 18 ; pub const I2C_CR2_FREQ_19MHZ : u32 = 19 ; pub const I2C_CR2_FREQ_20MHZ : u32 = 20 ; pub const I2C_CR2_FREQ_21MHZ : u32 = 21 ; pub const I2C_CR2_FREQ_22MHZ : u32 = 22 ; pub const I2C_CR2_FREQ_23MHZ : u32 = 23 ; pub const I2C_CR2_FREQ_24MHZ : u32 = 24 ; pub const I2C_CR2_FREQ_25MHZ : u32 = 25 ; pub const I2C_CR2_FREQ_26MHZ : u32 = 26 ; pub const I2C_CR2_FREQ_27MHZ : u32 = 27 ; pub const I2C_CR2_FREQ_28MHZ : u32 = 28 ; pub const I2C_CR2_FREQ_29MHZ : u32 = 29 ; pub const I2C_CR2_FREQ_30MHZ : u32 = 30 ; pub const I2C_CR2_FREQ_31MHZ : u32 = 31 ; pub const I2C_CR2_FREQ_32MHZ : u32 = 32 ; pub const I2C_CR2_FREQ_33MHZ : u32 = 33 ; pub const I2C_CR2_FREQ_34MHZ : u32 = 34 ; pub const I2C_CR2_FREQ_35MHZ : u32 = 35 ; pub const I2C_CR2_FREQ_36MHZ : u32 = 36 ; pub const I2C_CR2_FREQ_37MHZ : u32 = 37 ; pub const I2C_CR2_FREQ_38MHZ : u32 = 38 ; pub const I2C_CR2_FREQ_39MHZ : u32 = 39 ; pub const I2C_CR2_FREQ_40MHZ : u32 = 40 ; pub const I2C_CR2_FREQ_41MHZ : u32 = 41 ; pub const I2C_CR2_FREQ_42MHZ : u32 = 42 ; pub const I2C_OAR1_ADDMODE : u32 = 32768 ; pub const I2C_OAR1_ADDMODE_7BIT : u32 = 0 ; pub const I2C_OAR1_ADDMODE_10BIT : u32 = 1 ; pub const I2C_OAR2_ENDUAL : u32 = 1 ; pub const I2C_SR1_SMBALERT : u32 = 32768 ; pub const I2C_SR1_TIMEOUT : u32 = 16384 ; pub const I2C_SR1_PECERR : u32 = 4096 ; pub const I2C_SR1_OVR : u32 = 2048 ; pub const I2C_SR1_AF : u32 = 1024 ; pub const I2C_SR1_ARLO : u32 = 512 ; pub const I2C_SR1_BERR : u32 = 256 ; pub const I2C_SR1_TxE : u32 = 128 ; pub const I2C_SR1_RxNE : u32 = 64 ; pub const I2C_SR1_STOPF : u32 = 16 ; pub const I2C_SR1_ADD10 : u32 = 8 ; pub const I2C_SR1_BTF : u32 = 4 ; pub const I2C_SR1_ADDR : u32 = 2 ; pub const I2C_SR1_SB : u32 = 1 ; pub const I2C_SR2_DUALF : u32 = 128 ; pub const I2C_SR2_SMBHOST : u32 = 64 ; pub const I2C_SR2_SMBDEFAULT : u32 = 32 ; pub const I2C_SR2_GENCALL : u32 = 16 ; pub const I2C_SR2_TRA : u32 = 4 ; pub const I2C_SR2_BUSY : u32 = 2 ; pub const I2C_SR2_MSL : u32 = 1 ; pub const I2C_CCR_FS : u32 = 32768 ; pub const I2C_CCR_DUTY : u32 = 16384 ; pub const I2C_CCR_DUTY_DIV2 : u32 = 0 ; pub const I2C_CCR_DUTY_16_DIV_9 : u32 = 1 ; pub const I2C_WRITE : u32 = 0 ; pub const I2C_READ : u32 = 1 ; pub const IWDG_KR_RESET : u32 = 43690 ; pub const IWDG_KR_UNLOCK : u32 = 21845 ; pub const IWDG_KR_START : u32 = 52428 ; pub const IWDG_PR_LSB : u32 = 0 ; pub const IWDG_PR_DIV4 : u32 = 0 ; pub const IWDG_PR_DIV8 : u32 = 1 ; pub const IWDG_PR_DIV16 : u32 = 2 ; pub const IWDG_PR_DIV32 : u32 = 3 ; pub const IWDG_PR_DIV64 : u32 = 4 ; pub const IWDG_PR_DIV128 : u32 = 5 ; pub const IWDG_PR_DIV256 : u32 = 6 ; pub const IWDG_SR_RVU : u32 = 2 ; pub const IWDG_SR_PVU : u32 = 1 ; pub const PWR_CR_DBP : u32 = 256 ; pub const PWR_CR_PLS_LSB : u32 = 5 ; pub const PWR_CR_PLS_2V2 : u32 = 0 ; pub const PWR_CR_PLS_2V3 : u32 = 32 ; pub const PWR_CR_PLS_2V4 : u32 = 64 ; pub const PWR_CR_PLS_2V5 : u32 = 96 ; pub const PWR_CR_PLS_2V6 : u32 = 128 ; pub const PWR_CR_PLS_2V7 : u32 = 160 ; pub const PWR_CR_PLS_2V8 : u32 = 192 ; pub const PWR_CR_PLS_2V9 : u32 = 224 ; pub const PWR_CR_PLS_MASK : u32 = 224 ; pub const PWR_CR_PVDE : u32 = 16 ; pub const PWR_CR_CSBF : u32 = 8 ; pub const PWR_CR_CWUF : u32 = 4 ; pub const PWR_CR_PDDS : u32 = 2 ; pub const PWR_CR_LPDS : u32 = 1 ; pub const PWR_CSR_EWUP : u32 = 256 ; pub const PWR_CSR_PVDO : u32 = 4 ; pub const PWR_CSR_SBF : u32 = 2 ; pub const PWR_CSR_WUF : u32 = 1 ; pub const RCC_CR_PLL3RDY : u32 = 536870912 ; pub const RCC_CR_PLL3ON : u32 = 268435456 ; pub const RCC_CR_PLL2RDY : u32 = 134217728 ; pub const RCC_CR_PLL2ON : u32 = 67108864 ; pub const RCC_CR_PLLRDY : u32 = 33554432 ; pub const RCC_CR_PLLON : u32 = 16777216 ; pub const RCC_CR_CSSON : u32 = 524288 ; pub const RCC_CR_HSEBYP : u32 = 262144 ; pub const RCC_CR_HSERDY : u32 = 131072 ; pub const RCC_CR_HSEON : u32 = 65536 ; pub const RCC_CR_HSIRDY : u32 = 2 ; pub const RCC_CR_HSION : u32 = 1 ; pub const RCC_CFGR_OTGFSPRE : u32 = 4194304 ; pub const RCC_CFGR_USBPRE : u32 = 4194304 ; pub const RCC_CFGR_PLLMUL_SHIFT : u32 = 18 ; pub const RCC_CFGR_PLLMUL : u32 = 3932160 ; pub const RCC_CFGR_PLLXTPRE : u32 = 131072 ; pub const RCC_CFGR_PLLSRC : u32 = 65536 ; pub const RCC_CFGR_ADCPRE_SHIFT : u32 = 14 ; pub const RCC_CFGR_ADCPRE : u32 = 49152 ; pub const RCC_CFGR_PPRE2_SHIFT : u32 = 11 ; pub const RCC_CFGR_PPRE2 : u32 = 14336 ; pub const RCC_CFGR_PPRE1_SHIFT : u32 = 8 ; pub const RCC_CFGR_PPRE1 : u32 = 1792 ; pub const RCC_CFGR_HPRE_SHIFT : u32 = 4 ; pub const RCC_CFGR_HPRE : u32 = 240 ; pub const RCC_CFGR_SWS_SHIFT : u32 = 2 ; pub const RCC_CFGR_SWS : u32 = 12 ; pub const RCC_CFGR_SW_SHIFT : u32 = 0 ; pub const RCC_CFGR_SW : u32 = 3 ; pub const RCC_CFGR_MCO_SHIFT : u32 = 24 ; pub const RCC_CFGR_MCO_MASK : u32 = 15 ; pub const RCC_CFGR_MCO_NOCLK : u32 = 0 ; pub const RCC_CFGR_MCO_SYSCLK : u32 = 4 ; pub const RCC_CFGR_MCO_HSI : u32 = 5 ; pub const RCC_CFGR_MCO_HSE : u32 = 6 ; pub const RCC_CFGR_MCO_PLL_DIV2 : u32 = 7 ; pub const RCC_CFGR_MCO_PLL2 : u32 = 8 ; pub const RCC_CFGR_MCO_PLL3_DIV2 : u32 = 9 ; pub const RCC_CFGR_MCO_XT1 : u32 = 10 ; pub const RCC_CFGR_MCO_PLL3 : u32 = 11 ; pub const RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 : u32 = 0 ; pub const RCC_CFGR_USBPRE_PLL_CLK_NODIV : u32 = 1 ; pub const RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 : u32 = 0 ; pub const RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 : u32 = 1 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL2 : u32 = 0 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL3 : u32 = 1 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL4 : u32 = 2 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL5 : u32 = 3 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL6 : u32 = 4 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL7 : u32 = 5 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL8 : u32 = 6 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL9 : u32 = 7 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL10 : u32 = 8 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL11 : u32 = 9 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL12 : u32 = 10 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL13 : u32 = 11 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL14 : u32 = 12 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL15 : u32 = 13 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 : u32 = 13 ; pub const RCC_CFGR_PLLMUL_PLL_CLK_MUL16 : u32 = 14 ; pub const RCC_CFGR_PLLXTPRE_HSE_CLK : u32 = 0 ; pub const RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 : u32 = 1 ; pub const RCC_CFGR_PLLSRC_HSI_CLK_DIV2 : u32 = 0 ; pub const RCC_CFGR_PLLSRC_HSE_CLK : u32 = 1 ; pub const RCC_CFGR_PLLSRC_PREDIV1_CLK : u32 = 1 ; pub const RCC_CFGR_ADCPRE_PCLK2_DIV2 : u32 = 0 ; pub const RCC_CFGR_ADCPRE_PCLK2_DIV4 : u32 = 1 ; pub const RCC_CFGR_ADCPRE_PCLK2_DIV6 : u32 = 2 ; pub const RCC_CFGR_ADCPRE_PCLK2_DIV8 : u32 = 3 ; pub const RCC_CFGR_PPRE2_HCLK_NODIV : u32 = 0 ; pub const RCC_CFGR_PPRE2_HCLK_DIV2 : u32 = 4 ; pub const RCC_CFGR_PPRE2_HCLK_DIV4 : u32 = 5 ; pub const RCC_CFGR_PPRE2_HCLK_DIV8 : u32 = 6 ; pub const RCC_CFGR_PPRE2_HCLK_DIV16 : u32 = 7 ; pub const RCC_CFGR_PPRE1_HCLK_NODIV : u32 = 0 ; pub const RCC_CFGR_PPRE1_HCLK_DIV2 : u32 = 4 ; pub const RCC_CFGR_PPRE1_HCLK_DIV4 : u32 = 5 ; pub const RCC_CFGR_PPRE1_HCLK_DIV8 : u32 = 6 ; pub const RCC_CFGR_PPRE1_HCLK_DIV16 : u32 = 7 ; pub const RCC_CFGR_HPRE_SYSCLK_NODIV : u32 = 0 ; pub const RCC_CFGR_HPRE_SYSCLK_DIV2 : u32 = 8 ; pub const RCC_CFGR_HPRE_SYSCLK_DIV4 : u32 = 9 ; pub const RCC_CFGR_HPRE_SYSCLK_DIV8 : u32 = 10 ; pub const RCC_CFGR_HPRE_SYSCLK_DIV16 : u32 = 11 ; pub const RCC_CFGR_HPRE_SYSCLK_DIV64 : u32 = 12 ; pub const RCC_CFGR_HPRE_SYSCLK_DIV128 : u32 = 13 ; pub const RCC_CFGR_HPRE_SYSCLK_DIV256 : u32 = 14 ; pub const RCC_CFGR_HPRE_SYSCLK_DIV512 : u32 = 15 ; pub const RCC_CFGR_SWS_SYSCLKSEL_HSICLK : u32 = 0 ; pub const RCC_CFGR_SWS_SYSCLKSEL_HSECLK : u32 = 1 ; pub const RCC_CFGR_SWS_SYSCLKSEL_PLLCLK : u32 = 2 ; pub const RCC_CFGR_SW_SYSCLKSEL_HSICLK : u32 = 0 ; pub const RCC_CFGR_SW_SYSCLKSEL_HSECLK : u32 = 1 ; pub const RCC_CFGR_SW_SYSCLKSEL_PLLCLK : u32 = 2 ; pub const RCC_CIR_CSSC : u32 = 8388608 ; pub const RCC_CIR_PLL3RDYC : u32 = 4194304 ; pub const RCC_CIR_PLL2RDYC : u32 = 2097152 ; pub const RCC_CIR_PLLRDYC : u32 = 1048576 ; pub const RCC_CIR_HSERDYC : u32 = 524288 ; pub const RCC_CIR_HSIRDYC : u32 = 262144 ; pub const RCC_CIR_LSERDYC : u32 = 131072 ; pub const RCC_CIR_LSIRDYC : u32 = 65536 ; pub const RCC_CIR_PLL3RDYIE : u32 = 16384 ; pub const RCC_CIR_PLL2RDYIE : u32 = 8192 ; pub const RCC_CIR_PLLRDYIE : u32 = 4096 ; pub const RCC_CIR_HSERDYIE : u32 = 2048 ; pub const RCC_CIR_HSIRDYIE : u32 = 1024 ; pub const RCC_CIR_LSERDYIE : u32 = 512 ; pub const RCC_CIR_LSIRDYIE : u32 = 256 ; pub const RCC_CIR_CSSF : u32 = 128 ; pub const RCC_CIR_PLL3RDYF : u32 = 64 ; pub const RCC_CIR_PLL2RDYF : u32 = 32 ; pub const RCC_CIR_PLLRDYF : u32 = 16 ; pub const RCC_CIR_HSERDYF : u32 = 8 ; pub const RCC_CIR_HSIRDYF : u32 = 4 ; pub const RCC_CIR_LSERDYF : u32 = 2 ; pub const RCC_CIR_LSIRDYF : u32 = 1 ; pub const RCC_APB2RSTR_TIM17RST : u32 = 262144 ; pub const RCC_APB2RSTR_TIM16RST : u32 = 131072 ; pub const RCC_APB2RSTR_TIM15RST : u32 = 65536 ; pub const RCC_APB2RSTR_ADC3RST : u32 = 32768 ; pub const RCC_APB2RSTR_USART1RST : u32 = 16384 ; pub const RCC_APB2RSTR_TIM8RST : u32 = 8192 ; pub const RCC_APB2RSTR_SPI1RST : u32 = 4096 ; pub const RCC_APB2RSTR_TIM1RST : u32 = 2048 ; pub const RCC_APB2RSTR_ADC2RST : u32 = 1024 ; pub const RCC_APB2RSTR_ADC1RST : u32 = 512 ; pub const RCC_APB2RSTR_IOPGRST : u32 = 256 ; pub const RCC_APB2RSTR_IOPFRST : u32 = 128 ; pub const RCC_APB2RSTR_IOPERST : u32 = 64 ; pub const RCC_APB2RSTR_IOPDRST : u32 = 32 ; pub const RCC_APB2RSTR_IOPCRST : u32 = 16 ; pub const RCC_APB2RSTR_IOPBRST : u32 = 8 ; pub const RCC_APB2RSTR_IOPARST : u32 = 4 ; pub const RCC_APB2RSTR_AFIORST : u32 = 1 ; pub const RCC_APB1RSTR_DACRST : u32 = 536870912 ; pub const RCC_APB1RSTR_PWRRST : u32 = 268435456 ; pub const RCC_APB1RSTR_BKPRST : u32 = 134217728 ; pub const RCC_APB1RSTR_CAN2RST : u32 = 67108864 ; pub const RCC_APB1RSTR_CAN1RST : u32 = 33554432 ; pub const RCC_APB1RSTR_CANRST : u32 = 33554432 ; pub const RCC_APB1RSTR_USBRST : u32 = 8388608 ; pub const RCC_APB1RSTR_I2C2RST : u32 = 4194304 ; pub const RCC_APB1RSTR_I2C1RST : u32 = 2097152 ; pub const RCC_APB1RSTR_UART5RST : u32 = 1048576 ; pub const RCC_APB1RSTR_UART4RST : u32 = 524288 ; pub const RCC_APB1RSTR_USART3RST : u32 = 262144 ; pub const RCC_APB1RSTR_USART2RST : u32 = 131072 ; pub const RCC_APB1RSTR_SPI3RST : u32 = 32768 ; pub const RCC_APB1RSTR_SPI2RST : u32 = 16384 ; pub const RCC_APB1RSTR_WWDGRST : u32 = 2048 ; pub const RCC_APB1RSTR_TIM7RST : u32 = 32 ; pub const RCC_APB1RSTR_TIM6RST : u32 = 16 ; pub const RCC_APB1RSTR_TIM5RST : u32 = 8 ; pub const RCC_APB1RSTR_TIM4RST : u32 = 4 ; pub const RCC_APB1RSTR_TIM3RST : u32 = 2 ; pub const RCC_APB1RSTR_TIM2RST : u32 = 1 ; pub const RCC_AHBENR_ETHMACENRX : u32 = 65536 ; pub const RCC_AHBENR_ETHMACENTX : u32 = 32768 ; pub const RCC_AHBENR_ETHMACEN : u32 = 16384 ; pub const RCC_AHBENR_OTGFSEN : u32 = 4096 ; pub const RCC_AHBENR_SDIOEN : u32 = 1024 ; pub const RCC_AHBENR_FSMCEN : u32 = 256 ; pub const RCC_AHBENR_CRCEN : u32 = 64 ; pub const RCC_AHBENR_FLITFEN : u32 = 16 ; pub const RCC_AHBENR_SRAMEN : u32 = 4 ; pub const RCC_AHBENR_DMA2EN : u32 = 2 ; pub const RCC_AHBENR_DMA1EN : u32 = 1 ; pub const RCC_APB2ENR_TIM17EN : u32 = 262144 ; pub const RCC_APB2ENR_TIM16EN : u32 = 131072 ; pub const RCC_APB2ENR_TIM15EN : u32 = 65536 ; pub const RCC_APB2ENR_ADC3EN : u32 = 32768 ; pub const RCC_APB2ENR_USART1EN : u32 = 16384 ; pub const RCC_APB2ENR_TIM8EN : u32 = 8192 ; pub const RCC_APB2ENR_SPI1EN : u32 = 4096 ; pub const RCC_APB2ENR_TIM1EN : u32 = 2048 ; pub const RCC_APB2ENR_ADC2EN : u32 = 1024 ; pub const RCC_APB2ENR_ADC1EN : u32 = 512 ; pub const RCC_APB2ENR_IOPGEN : u32 = 256 ; pub const RCC_APB2ENR_IOPFEN : u32 = 128 ; pub const RCC_APB2ENR_IOPEEN : u32 = 64 ; pub const RCC_APB2ENR_IOPDEN : u32 = 32 ; pub const RCC_APB2ENR_IOPCEN : u32 = 16 ; pub const RCC_APB2ENR_IOPBEN : u32 = 8 ; pub const RCC_APB2ENR_IOPAEN : u32 = 4 ; pub const RCC_APB2ENR_AFIOEN : u32 = 1 ; pub const RCC_APB1ENR_DACEN : u32 = 536870912 ; pub const RCC_APB1ENR_PWREN : u32 = 268435456 ; pub const RCC_APB1ENR_BKPEN : u32 = 134217728 ; pub const RCC_APB1ENR_CAN2EN : u32 = 67108864 ; pub const RCC_APB1ENR_CAN1EN : u32 = 33554432 ; pub const RCC_APB1ENR_CANEN : u32 = 33554432 ; pub const RCC_APB1ENR_USBEN : u32 = 8388608 ; pub const RCC_APB1ENR_I2C2EN : u32 = 4194304 ; pub const RCC_APB1ENR_I2C1EN : u32 = 2097152 ; pub const RCC_APB1ENR_UART5EN : u32 = 1048576 ; pub const RCC_APB1ENR_UART4EN : u32 = 524288 ; pub const RCC_APB1ENR_USART3EN : u32 = 262144 ; pub const RCC_APB1ENR_USART2EN : u32 = 131072 ; pub const RCC_APB1ENR_SPI3EN : u32 = 32768 ; pub const RCC_APB1ENR_SPI2EN : u32 = 16384 ; pub const RCC_APB1ENR_WWDGEN : u32 = 2048 ; pub const RCC_APB1ENR_TIM7EN : u32 = 32 ; pub const RCC_APB1ENR_TIM6EN : u32 = 16 ; pub const RCC_APB1ENR_TIM5EN : u32 = 8 ; pub const RCC_APB1ENR_TIM4EN : u32 = 4 ; pub const RCC_APB1ENR_TIM3EN : u32 = 2 ; pub const RCC_APB1ENR_TIM2EN : u32 = 1 ; pub const RCC_BDCR_BDRST : u32 = 65536 ; pub const RCC_BDCR_RTCEN : u32 = 32768 ; pub const RCC_BDCR_LSEBYP : u32 = 4 ; pub const RCC_BDCR_LSERDY : u32 = 2 ; pub const RCC_BDCR_LSEON : u32 = 1 ; pub const RCC_CSR_LPWRRSTF : u32 = 2147483648 ; pub const RCC_CSR_WWDGRSTF : u32 = 1073741824 ; pub const RCC_CSR_IWDGRSTF : u32 = 536870912 ; pub const RCC_CSR_SFTRSTF : u32 = 268435456 ; pub const RCC_CSR_PORRSTF : u32 = 134217728 ; pub const RCC_CSR_PINRSTF : u32 = 67108864 ; pub const RCC_CSR_RMVF : u32 = 16777216 ; pub const RCC_CSR_RESET_FLAGS : u32 = 4227858432 ; pub const RCC_CSR_LSIRDY : u32 = 2 ; pub const RCC_CSR_LSION : u32 = 1 ; pub const RCC_AHBRSTR_ETHMACRST : u32 = 16384 ; pub const RCC_AHBRSTR_OTGFSRST : u32 = 4096 ; pub const RCC_CFGR2_I2S3SRC_SYSCLK : u32 = 0 ; pub const RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK : u32 = 1 ; pub const RCC_CFGR2_I2S2SRC_SYSCLK : u32 = 0 ; pub const RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK : u32 = 1 ; pub const RCC_CFGR2_I2S2SRC : u32 = 131072 ; pub const RCC_CFGR2_PREDIV1SRC_HSE_CLK : u32 = 0 ; pub const RCC_CFGR2_PREDIV1SRC_PLL2_CLK : u32 = 1 ; pub const RCC_CFGR2_PREDIV1SRC : u32 = 65536 ; pub const RCC_CFGR2_PLL3MUL_SHIFT : u32 = 12 ; pub const RCC_CFGR2_PLL3MUL : u32 = 61440 ; pub const RCC_CFGR2_PLL2MUL_SHIFT : u32 = 8 ; pub const RCC_CFGR2_PLL2MUL : u32 = 3840 ; pub const RCC_CFGR2_PREDIV2_SHIFT : u32 = 4 ; pub const RCC_CFGR2_PREDIV2 : u32 = 240 ; pub const RCC_CFGR2_PREDIV1_SHIFT : u32 = 0 ; pub const RCC_CFGR2_PREDIV1 : u32 = 15 ; pub const RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 : u32 = 6 ; pub const RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 : u32 = 7 ; pub const RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 : u32 = 8 ; pub const RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 : u32 = 9 ; pub const RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 : u32 = 10 ; pub const RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 : u32 = 11 ; pub const RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 : u32 = 12 ; pub const RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 : u32 = 14 ; pub const RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 : u32 = 15 ; pub const RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 : u32 = 6 ; pub const RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 : u32 = 7 ; pub const RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 : u32 = 8 ; pub const RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 : u32 = 9 ; pub const RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 : u32 = 10 ; pub const RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 : u32 = 11 ; pub const RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 : u32 = 12 ; pub const RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 : u32 = 14 ; pub const RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 : u32 = 15 ; pub const RCC_CFGR2_PREDIV_NODIV : u32 = 0 ; pub const RCC_CFGR2_PREDIV_DIV2 : u32 = 1 ; pub const RCC_CFGR2_PREDIV_DIV3 : u32 = 2 ; pub const RCC_CFGR2_PREDIV_DIV4 : u32 = 3 ; pub const RCC_CFGR2_PREDIV_DIV5 : u32 = 4 ; pub const RCC_CFGR2_PREDIV_DIV6 : u32 = 5 ; pub const RCC_CFGR2_PREDIV_DIV7 : u32 = 6 ; pub const RCC_CFGR2_PREDIV_DIV8 : u32 = 7 ; pub const RCC_CFGR2_PREDIV_DIV9 : u32 = 8 ; pub const RCC_CFGR2_PREDIV_DIV10 : u32 = 9 ; pub const RCC_CFGR2_PREDIV_DIV11 : u32 = 10 ; pub const RCC_CFGR2_PREDIV_DIV12 : u32 = 11 ; pub const RCC_CFGR2_PREDIV_DIV13 : u32 = 12 ; pub const RCC_CFGR2_PREDIV_DIV14 : u32 = 13 ; pub const RCC_CFGR2_PREDIV_DIV15 : u32 = 14 ; pub const RCC_CFGR2_PREDIV_DIV16 : u32 = 15 ; pub const RCC_CFGR2_PREDIV2_NODIV : u32 = 0 ; pub const RCC_CFGR2_PREDIV2_DIV2 : u32 = 1 ; pub const RCC_CFGR2_PREDIV2_DIV3 : u32 = 2 ; pub const RCC_CFGR2_PREDIV2_DIV4 : u32 = 3 ; pub const RCC_CFGR2_PREDIV2_DIV5 : u32 = 4 ; pub const RCC_CFGR2_PREDIV2_DIV6 : u32 = 5 ; pub const RCC_CFGR2_PREDIV2_DIV7 : u32 = 6 ; pub const RCC_CFGR2_PREDIV2_DIV8 : u32 = 7 ; pub const RCC_CFGR2_PREDIV2_DIV9 : u32 = 8 ; pub const RCC_CFGR2_PREDIV2_DIV10 : u32 = 9 ; pub const RCC_CFGR2_PREDIV2_DIV11 : u32 = 10 ; pub const RCC_CFGR2_PREDIV2_DIV12 : u32 = 11 ; pub const RCC_CFGR2_PREDIV2_DIV13 : u32 = 12 ; pub const RCC_CFGR2_PREDIV2_DIV14 : u32 = 13 ; pub const RCC_CFGR2_PREDIV2_DIV15 : u32 = 14 ; pub const RCC_CFGR2_PREDIV2_DIV16 : u32 = 15 ; pub const RTC_CRH_OWIE : u32 = 4 ; pub const RTC_CRH_ALRIE : u32 = 2 ; pub const RTC_CRH_SECIE : u32 = 1 ; pub const RTC_CRL_RTOFF : u32 = 32 ; pub const RTC_CRL_CNF : u32 = 16 ; pub const RTC_CRL_RSF : u32 = 8 ; pub const RTC_CRL_OWF : u32 = 4 ; pub const RTC_CRL_ALRF : u32 = 2 ; pub const RTC_CRL_SECF : u32 = 1 ; pub const SPI1 : u32 = 1073819648 ; pub const SPI2 : u32 = 1073756160 ; pub const SPI3 : u32 = 1073757184 ; pub const SPI_CR1_BIDIMODE_2LINE_UNIDIR : u32 = 0 ; pub const SPI_CR1_BIDIMODE_1LINE_BIDIR : u32 = 32768 ; pub const SPI_CR1_BIDIMODE : u32 = 32768 ; pub const SPI_CR1_BIDIOE : u32 = 16384 ; pub const SPI_CR1_CRCEN : u32 = 8192 ; pub const SPI_CR1_CRCNEXT : u32 = 4096 ; pub const SPI_CR1_RXONLY : u32 = 1024 ; pub const SPI_CR1_SSM : u32 = 512 ; pub const SPI_CR1_SSI : u32 = 256 ; pub const SPI_CR1_MSBFIRST : u32 = 0 ; pub const SPI_CR1_LSBFIRST : u32 = 128 ; pub const SPI_CR1_SPE : u32 = 64 ; pub const SPI_CR1_BAUDRATE_FPCLK_DIV_2 : u32 = 0 ; pub const SPI_CR1_BAUDRATE_FPCLK_DIV_4 : u32 = 8 ; pub const SPI_CR1_BAUDRATE_FPCLK_DIV_8 : u32 = 16 ; pub const SPI_CR1_BAUDRATE_FPCLK_DIV_16 : u32 = 24 ; pub const SPI_CR1_BAUDRATE_FPCLK_DIV_32 : u32 = 32 ; pub const SPI_CR1_BAUDRATE_FPCLK_DIV_64 : u32 = 40 ; pub const SPI_CR1_BAUDRATE_FPCLK_DIV_128 : u32 = 48 ; pub const SPI_CR1_BAUDRATE_FPCLK_DIV_256 : u32 = 56 ; pub const SPI_CR1_BR_FPCLK_DIV_2 : u32 = 0 ; pub const SPI_CR1_BR_FPCLK_DIV_4 : u32 = 1 ; pub const SPI_CR1_BR_FPCLK_DIV_8 : u32 = 2 ; pub const SPI_CR1_BR_FPCLK_DIV_16 : u32 = 3 ; pub const SPI_CR1_BR_FPCLK_DIV_32 : u32 = 4 ; pub const SPI_CR1_BR_FPCLK_DIV_64 : u32 = 5 ; pub const SPI_CR1_BR_FPCLK_DIV_128 : u32 = 6 ; pub const SPI_CR1_BR_FPCLK_DIV_256 : u32 = 7 ; pub const SPI_CR1_MSTR : u32 = 4 ; pub const SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE : u32 = 0 ; pub const SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE : u32 = 2 ; pub const SPI_CR1_CPOL : u32 = 2 ; pub const SPI_CR1_CPHA_CLK_TRANSITION_1 : u32 = 0 ; pub const SPI_CR1_CPHA_CLK_TRANSITION_2 : u32 = 1 ; pub const SPI_CR1_CPHA : u32 = 1 ; pub const SPI_CR2_TXEIE : u32 = 128 ; pub const SPI_CR2_RXNEIE : u32 = 64 ; pub const SPI_CR2_ERRIE : u32 = 32 ; pub const SPI_CR2_SSOE : u32 = 4 ; pub const SPI_CR2_TXDMAEN : u32 = 2 ; pub const SPI_CR2_RXDMAEN : u32 = 1 ; pub const SPI_SR_BSY : u32 = 128 ; pub const SPI_SR_OVR : u32 = 64 ; pub const SPI_SR_MODF : u32 = 32 ; pub const SPI_SR_CRCERR : u32 = 16 ; pub const SPI_SR_UDR : u32 = 8 ; pub const SPI_SR_CHSIDE : u32 = 4 ; pub const SPI_SR_TXE : u32 = 2 ; pub const SPI_SR_RXNE : u32 = 1 ; pub const SPI_I2SCFGR_I2SMOD : u32 = 2048 ; pub const SPI_I2SCFGR_I2SE : u32 = 1024 ; pub const SPI_I2SCFGR_I2SCFG_LSB : u32 = 8 ; pub const SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT : u32 = 0 ; pub const SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE : u32 = 1 ; pub const SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT : u32 = 2 ; pub const SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE : u32 = 3 ; pub const SPI_I2SCFGR_PCMSYNC : u32 = 128 ; pub const SPI_I2SCFGR_I2SSTD_LSB : u32 = 4 ; pub const SPI_I2SCFGR_I2SSTD_I2S_PHILIPS : u32 = 0 ; pub const SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED : u32 = 1 ; pub const SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED : u32 = 2 ; pub const SPI_I2SCFGR_I2SSTD_PCM : u32 = 3 ; pub const SPI_I2SCFGR_CKPOL : u32 = 8 ; pub const SPI_I2SCFGR_DATLEN_LSB : u32 = 1 ; pub const SPI_I2SCFGR_DATLEN_16BIT : u32 = 0 ; pub const SPI_I2SCFGR_DATLEN_24BIT : u32 = 1 ; pub const SPI_I2SCFGR_DATLEN_32BIT : u32 = 2 ; pub const SPI_I2SCFGR_CHLEN : u32 = 1 ; pub const SPI_I2SPR_MCKOE : u32 = 512 ; pub const SPI_I2SPR_ODD : u32 = 256 ; pub const SPI_CR1_DFF_8BIT : u32 = 0 ; pub const SPI_CR1_DFF_16BIT : u32 = 2048 ; pub const SPI_CR1_DFF : u32 = 2048 ; pub const USB_CNTR_CTRM : u32 = 32768 ; pub const USB_CNTR_PMAOVRM : u32 = 16384 ; pub const USB_CNTR_ERRM : u32 = 8192 ; pub const USB_CNTR_WKUPM : u32 = 4096 ; pub const USB_CNTR_SUSPM : u32 = 2048 ; pub const USB_CNTR_RESETM : u32 = 1024 ; pub const USB_CNTR_SOFM : u32 = 512 ; pub const USB_CNTR_ESOFM : u32 = 256 ; pub const USB_CNTR_RESUME : u32 = 16 ; pub const USB_CNTR_FSUSP : u32 = 8 ; pub const USB_CNTR_LP_MODE : u32 = 4 ; pub const USB_CNTR_PWDN : u32 = 2 ; pub const USB_CNTR_FRES : u32 = 1 ; pub const USB_ISTR_CTR : u32 = 32768 ; pub const USB_ISTR_PMAOVR : u32 = 16384 ; pub const USB_ISTR_ERR : u32 = 8192 ; pub const USB_ISTR_WKUP : u32 = 4096 ; pub const USB_ISTR_SUSP : u32 = 2048 ; pub const USB_ISTR_RESET : u32 = 1024 ; pub const USB_ISTR_SOF : u32 = 512 ; pub const USB_ISTR_ESOF : u32 = 256 ; pub const USB_ISTR_DIR : u32 = 16 ; pub const USB_ISTR_EP_ID : u32 = 15 ; pub const USB_FNR_RXDP : u32 = 32768 ; pub const USB_FNR_RXDM : u32 = 16384 ; pub const USB_FNR_LCK : u32 = 8192 ; pub const USB_FNR_LSOF_SHIFT : u32 = 11 ; pub const USB_FNR_LSOF : u32 = 6144 ; pub const USB_FNR_FN : u32 = 2047 ; pub const USB_DADDR_EF : u32 = 128 ; pub const USB_DADDR_ADDR : u32 = 127 ; pub const USB_BTABLE_BTABLE : u32 = 65528 ; pub const USB_EP0 : u32 = 0 ; pub const USB_EP1 : u32 = 1 ; pub const USB_EP2 : u32 = 2 ; pub const USB_EP3 : u32 = 3 ; pub const USB_EP4 : u32 = 4 ; pub const USB_EP5 : u32 = 5 ; pub const USB_EP6 : u32 = 6 ; pub const USB_EP7 : u32 = 7 ; pub const USB_EP_RX_CTR : u32 = 32768 ; pub const USB_EP_RX_DTOG : u32 = 16384 ; pub const USB_EP_RX_STAT : u32 = 12288 ; pub const USB_EP_SETUP : u32 = 2048 ; pub const USB_EP_TYPE : u32 = 1536 ; pub const USB_EP_KIND : u32 = 256 ; pub const USB_EP_TX_CTR : u32 = 128 ; pub const USB_EP_TX_DTOG : u32 = 64 ; pub const USB_EP_TX_STAT : u32 = 48 ; pub const USB_EP_ADDR : u32 = 15 ; pub const USB_EP_NTOGGLE_MSK : u32 = 36751 ; pub const USB_EP_RX_STAT_TOG_MSK : u32 = 49039 ; pub const USB_EP_TX_STAT_TOG_MSK : u32 = 36799 ; pub const USB_EP_RX_STAT_DISABLED : u32 = 0 ; pub const USB_EP_RX_STAT_STALL : u32 = 4096 ; pub const USB_EP_RX_STAT_NAK : u32 = 8192 ; pub const USB_EP_RX_STAT_VALID : u32 = 12288 ; pub const USB_EP_TX_STAT_DISABLED : u32 = 0 ; pub const USB_EP_TX_STAT_STALL : u32 = 16 ; pub const USB_EP_TX_STAT_NAK : u32 = 32 ; pub const USB_EP_TX_STAT_VALID : u32 = 48 ; pub const USB_EP_TYPE_BULK : u32 = 0 ; pub const USB_EP_TYPE_CONTROL : u32 = 512 ; pub const USB_EP_TYPE_ISO : u32 = 1024 ; pub const USB_EP_TYPE_INTERRUPT : u32 = 1536 ; pub const TIM1 : u32 = 1073818624 ; pub const TIM2 : u32 = 1073741824 ; pub const TIM3 : u32 = 1073742848 ; pub const TIM4 : u32 = 1073743872 ; pub const TIM5 : u32 = 1073744896 ; pub const TIM6 : u32 = 1073745920 ; pub const TIM7 : u32 = 1073746944 ; pub const TIM8 : u32 = 1073820672 ; pub const TIM9 : u32 = 1073826816 ; pub const TIM10 : u32 = 1073827840 ; pub const TIM11 : u32 = 1073828864 ; pub const TIM12 : u32 = 1073747968 ; pub const TIM13 : u32 = 1073748992 ; pub const TIM14 : u32 = 1073750016 ; pub const TIM15 : u32 = 1073823744 ; pub const TIM16 : u32 = 1073824768 ; pub const TIM17 : u32 = 1073825792 ; pub const TIM_CR1_CKD_CK_INT : u32 = 0 ; pub const TIM_CR1_CKD_CK_INT_MUL_2 : u32 = 256 ; pub const TIM_CR1_CKD_CK_INT_MUL_4 : u32 = 512 ; pub const TIM_CR1_CKD_CK_INT_MASK : u32 = 768 ; pub const TIM_CR1_ARPE : u32 = 128 ; pub const TIM_CR1_CMS_EDGE : u32 = 0 ; pub const TIM_CR1_CMS_CENTER_1 : u32 = 32 ; pub const TIM_CR1_CMS_CENTER_2 : u32 = 64 ; pub const TIM_CR1_CMS_CENTER_3 : u32 = 96 ; pub const TIM_CR1_CMS_MASK : u32 = 96 ; pub const TIM_CR1_DIR_UP : u32 = 0 ; pub const TIM_CR1_DIR_DOWN : u32 = 16 ; pub const TIM_CR1_OPM : u32 = 8 ; pub const TIM_CR1_URS : u32 = 4 ; pub const TIM_CR1_UDIS : u32 = 2 ; pub const TIM_CR1_CEN : u32 = 1 ; pub const TIM_CR2_OIS4 : u32 = 16384 ; pub const TIM_CR2_OIS3N : u32 = 8192 ; pub const TIM_CR2_OIS3 : u32 = 4096 ; pub const TIM_CR2_OIS2N : u32 = 2048 ; pub const TIM_CR2_OIS2 : u32 = 1024 ; pub const TIM_CR2_OIS1N : u32 = 512 ; pub const TIM_CR2_OIS1 : u32 = 256 ; pub const TIM_CR2_OIS_MASK : u32 = 32512 ; pub const TIM_CR2_TI1S : u32 = 128 ; pub const TIM_CR2_MMS_RESET : u32 = 0 ; pub const TIM_CR2_MMS_ENABLE : u32 = 16 ; pub const TIM_CR2_MMS_UPDATE : u32 = 32 ; pub const TIM_CR2_MMS_COMPARE_PULSE : u32 = 48 ; pub const TIM_CR2_MMS_COMPARE_OC1REF : u32 = 64 ; pub const TIM_CR2_MMS_COMPARE_OC2REF : u32 = 80 ; pub const TIM_CR2_MMS_COMPARE_OC3REF : u32 = 96 ; pub const TIM_CR2_MMS_COMPARE_OC4REF : u32 = 112 ; pub const TIM_CR2_MMS_MASK : u32 = 112 ; pub const TIM_CR2_CCDS : u32 = 8 ; pub const TIM_CR2_CCUS : u32 = 4 ; pub const TIM_CR2_CCPC : u32 = 1 ; pub const TIM_SMCR_ETP : u32 = 32768 ; pub const TIM_SMCR_ECE : u32 = 16384 ; pub const TIM_SMCR_ETPS_OFF : u32 = 0 ; pub const TIM_SMCR_ETPS_ETRP_DIV_2 : u32 = 4096 ; pub const TIM_SMCR_ETPS_ETRP_DIV_4 : u32 = 8192 ; pub const TIM_SMCR_ETPS_ETRP_DIV_8 : u32 = 12288 ; pub const TIM_SMCR_ETF_OFF : u32 = 0 ; pub const TIM_SMCR_ETF_CK_INT_N_2 : u32 = 256 ; pub const TIM_SMCR_ETF_CK_INT_N_4 : u32 = 512 ; pub const TIM_SMCR_ETF_CK_INT_N_8 : u32 = 768 ; pub const TIM_SMCR_ETF_DTS_DIV_2_N_6 : u32 = 1024 ; pub const TIM_SMCR_ETF_DTS_DIV_2_N_8 : u32 = 1280 ; pub const TIM_SMCR_ETF_DTS_DIV_4_N_6 : u32 = 1536 ; pub const TIM_SMCR_ETF_DTS_DIV_4_N_8 : u32 = 1792 ; pub const TIM_SMCR_ETF_DTS_DIV_8_N_6 : u32 = 2048 ; pub const TIM_SMCR_ETF_DTS_DIV_8_N_8 : u32 = 2304 ; pub const TIM_SMCR_ETF_DTS_DIV_16_N_5 : u32 = 2560 ; pub const TIM_SMCR_ETF_DTS_DIV_16_N_6 : u32 = 2816 ; pub const TIM_SMCR_ETF_DTS_DIV_16_N_8 : u32 = 3072 ; pub const TIM_SMCR_ETF_DTS_DIV_32_N_5 : u32 = 3328 ; pub const TIM_SMCR_ETF_DTS_DIV_32_N_6 : u32 = 3584 ; pub const TIM_SMCR_ETF_DTS_DIV_32_N_8 : u32 = 3840 ; pub const TIM_SMCR_ETF_MASK : u32 = 3840 ; pub const TIM_SMCR_MSM : u32 = 128 ; pub const TIM_SMCR_TS_ITR0 : u32 = 0 ; pub const TIM_SMCR_TS_ITR1 : u32 = 16 ; pub const TIM_SMCR_TS_ITR2 : u32 = 32 ; pub const TIM_SMCR_TS_ITR3 : u32 = 48 ; pub const TIM_SMCR_TS_TI1F_ED : u32 = 64 ; pub const TIM_SMCR_TS_TI1FP1 : u32 = 80 ; pub const TIM_SMCR_TS_TI2FP2 : u32 = 96 ; pub const TIM_SMCR_TS_ETRF : u32 = 112 ; pub const TIM_SMCR_TS_MASK : u32 = 112 ; pub const TIM_SMCR_SMS_OFF : u32 = 0 ; pub const TIM_SMCR_SMS_EM1 : u32 = 1 ; pub const TIM_SMCR_SMS_EM2 : u32 = 2 ; pub const TIM_SMCR_SMS_EM3 : u32 = 3 ; pub const TIM_SMCR_SMS_RM : u32 = 4 ; pub const TIM_SMCR_SMS_GM : u32 = 5 ; pub const TIM_SMCR_SMS_TM : u32 = 6 ; pub const TIM_SMCR_SMS_ECM1 : u32 = 7 ; pub const TIM_SMCR_SMS_MASK : u32 = 7 ; pub const TIM_DIER_TDE : u32 = 16384 ; pub const TIM_DIER_COMDE : u32 = 8192 ; pub const TIM_DIER_CC4DE : u32 = 4096 ; pub const TIM_DIER_CC3DE : u32 = 2048 ; pub const TIM_DIER_CC2DE : u32 = 1024 ; pub const TIM_DIER_CC1DE : u32 = 512 ; pub const TIM_DIER_UDE : u32 = 256 ; pub const TIM_DIER_BIE : u32 = 128 ; pub const TIM_DIER_TIE : u32 = 64 ; pub const TIM_DIER_COMIE : u32 = 32 ; pub const TIM_DIER_CC4IE : u32 = 16 ; pub const TIM_DIER_CC3IE : u32 = 8 ; pub const TIM_DIER_CC2IE : u32 = 4 ; pub const TIM_DIER_CC1IE : u32 = 2 ; pub const TIM_DIER_UIE : u32 = 1 ; pub const TIM_SR_CC4OF : u32 = 4096 ; pub const TIM_SR_CC3OF : u32 = 2048 ; pub const TIM_SR_CC2OF : u32 = 1024 ; pub const TIM_SR_CC1OF : u32 = 512 ; pub const TIM_SR_BIF : u32 = 128 ; pub const TIM_SR_TIF : u32 = 64 ; pub const TIM_SR_COMIF : u32 = 32 ; pub const TIM_SR_CC4IF : u32 = 16 ; pub const TIM_SR_CC3IF : u32 = 8 ; pub const TIM_SR_CC2IF : u32 = 4 ; pub const TIM_SR_CC1IF : u32 = 2 ; pub const TIM_SR_UIF : u32 = 1 ; pub const TIM_EGR_BG : u32 = 128 ; pub const TIM_EGR_TG : u32 = 64 ; pub const TIM_EGR_COMG : u32 = 32 ; pub const TIM_EGR_CC4G : u32 = 16 ; pub const TIM_EGR_CC3G : u32 = 8 ; pub const TIM_EGR_CC2G : u32 = 4 ; pub const TIM_EGR_CC1G : u32 = 2 ; pub const TIM_EGR_UG : u32 = 1 ; pub const TIM_CCMR1_OC2CE : u32 = 32768 ; pub const TIM_CCMR1_OC2M_FROZEN : u32 = 0 ; pub const TIM_CCMR1_OC2M_ACTIVE : u32 = 4096 ; pub const TIM_CCMR1_OC2M_INACTIVE : u32 = 8192 ; pub const TIM_CCMR1_OC2M_TOGGLE : u32 = 12288 ; pub const TIM_CCMR1_OC2M_FORCE_LOW : u32 = 16384 ; pub const TIM_CCMR1_OC2M_FORCE_HIGH : u32 = 20480 ; pub const TIM_CCMR1_OC2M_PWM1 : u32 = 24576 ; pub const TIM_CCMR1_OC2M_PWM2 : u32 = 28672 ; pub const TIM_CCMR1_OC2M_MASK : u32 = 28672 ; pub const TIM_CCMR1_OC2PE : u32 = 2048 ; pub const TIM_CCMR1_OC2FE : u32 = 1024 ; pub const TIM_CCMR1_CC2S_OUT : u32 = 0 ; pub const TIM_CCMR1_CC2S_IN_TI2 : u32 = 256 ; pub const TIM_CCMR1_CC2S_IN_TI1 : u32 = 512 ; pub const TIM_CCMR1_CC2S_IN_TRC : u32 = 768 ; pub const TIM_CCMR1_CC2S_MASK : u32 = 768 ; pub const TIM_CCMR1_OC1CE : u32 = 128 ; pub const TIM_CCMR1_OC1M_FROZEN : u32 = 0 ; pub const TIM_CCMR1_OC1M_ACTIVE : u32 = 16 ; pub const TIM_CCMR1_OC1M_INACTIVE : u32 = 32 ; pub const TIM_CCMR1_OC1M_TOGGLE : u32 = 48 ; pub const TIM_CCMR1_OC1M_FORCE_LOW : u32 = 64 ; pub const TIM_CCMR1_OC1M_FORCE_HIGH : u32 = 80 ; pub const TIM_CCMR1_OC1M_PWM1 : u32 = 96 ; pub const TIM_CCMR1_OC1M_PWM2 : u32 = 112 ; pub const TIM_CCMR1_OC1M_MASK : u32 = 112 ; pub const TIM_CCMR1_OC1PE : u32 = 8 ; pub const TIM_CCMR1_OC1FE : u32 = 4 ; pub const TIM_CCMR1_CC1S_OUT : u32 = 0 ; pub const TIM_CCMR1_CC1S_IN_TI2 : u32 = 2 ; pub const TIM_CCMR1_CC1S_IN_TI1 : u32 = 1 ; pub const TIM_CCMR1_CC1S_IN_TRC : u32 = 3 ; pub const TIM_CCMR1_CC1S_MASK : u32 = 3 ; pub const TIM_CCMR1_IC2F_OFF : u32 = 0 ; pub const TIM_CCMR1_IC2F_CK_INT_N_2 : u32 = 4096 ; pub const TIM_CCMR1_IC2F_CK_INT_N_4 : u32 = 8192 ; pub const TIM_CCMR1_IC2F_CK_INT_N_8 : u32 = 12288 ; pub const TIM_CCMR1_IC2F_DTF_DIV_2_N_6 : u32 = 16384 ; pub const TIM_CCMR1_IC2F_DTF_DIV_2_N_8 : u32 = 20480 ; pub const TIM_CCMR1_IC2F_DTF_DIV_4_N_6 : u32 = 24576 ; pub const TIM_CCMR1_IC2F_DTF_DIV_4_N_8 : u32 = 28672 ; pub const TIM_CCMR1_IC2F_DTF_DIV_8_N_6 : u32 = 32768 ; pub const TIM_CCMR1_IC2F_DTF_DIV_8_N_8 : u32 = 36864 ; pub const TIM_CCMR1_IC2F_DTF_DIV_16_N_5 : u32 = 40960 ; pub const TIM_CCMR1_IC2F_DTF_DIV_16_N_6 : u32 = 45056 ; pub const TIM_CCMR1_IC2F_DTF_DIV_16_N_8 : u32 = 49152 ; pub const TIM_CCMR1_IC2F_DTF_DIV_32_N_5 : u32 = 53248 ; pub const TIM_CCMR1_IC2F_DTF_DIV_32_N_6 : u32 = 57344 ; pub const TIM_CCMR1_IC2F_DTF_DIV_32_N_8 : u32 = 61440 ; pub const TIM_CCMR1_IC2F_MASK : u32 = 61440 ; pub const TIM_CCMR1_IC2PSC_OFF : u32 = 0 ; pub const TIM_CCMR1_IC2PSC_2 : u32 = 1024 ; pub const TIM_CCMR1_IC2PSC_4 : u32 = 2048 ; pub const TIM_CCMR1_IC2PSC_8 : u32 = 3072 ; pub const TIM_CCMR1_IC2PSC_MASK : u32 = 3072 ; pub const TIM_CCMR1_IC1F_OFF : u32 = 0 ; pub const TIM_CCMR1_IC1F_CK_INT_N_2 : u32 = 16 ; pub const TIM_CCMR1_IC1F_CK_INT_N_4 : u32 = 32 ; pub const TIM_CCMR1_IC1F_CK_INT_N_8 : u32 = 48 ; pub const TIM_CCMR1_IC1F_DTF_DIV_2_N_6 : u32 = 64 ; pub const TIM_CCMR1_IC1F_DTF_DIV_2_N_8 : u32 = 80 ; pub const TIM_CCMR1_IC1F_DTF_DIV_4_N_6 : u32 = 96 ; pub const TIM_CCMR1_IC1F_DTF_DIV_4_N_8 : u32 = 112 ; pub const TIM_CCMR1_IC1F_DTF_DIV_8_N_6 : u32 = 128 ; pub const TIM_CCMR1_IC1F_DTF_DIV_8_N_8 : u32 = 144 ; pub const TIM_CCMR1_IC1F_DTF_DIV_16_N_5 : u32 = 160 ; pub const TIM_CCMR1_IC1F_DTF_DIV_16_N_6 : u32 = 176 ; pub const TIM_CCMR1_IC1F_DTF_DIV_16_N_8 : u32 = 192 ; pub const TIM_CCMR1_IC1F_DTF_DIV_32_N_5 : u32 = 208 ; pub const TIM_CCMR1_IC1F_DTF_DIV_32_N_6 : u32 = 224 ; pub const TIM_CCMR1_IC1F_DTF_DIV_32_N_8 : u32 = 240 ; pub const TIM_CCMR1_IC1F_MASK : u32 = 240 ; pub const TIM_CCMR1_IC1PSC_OFF : u32 = 0 ; pub const TIM_CCMR1_IC1PSC_2 : u32 = 4 ; pub const TIM_CCMR1_IC1PSC_4 : u32 = 8 ; pub const TIM_CCMR1_IC1PSC_8 : u32 = 12 ; pub const TIM_CCMR1_IC1PSC_MASK : u32 = 12 ; pub const TIM_CCMR2_OC4CE : u32 = 32768 ; pub const TIM_CCMR2_OC4M_FROZEN : u32 = 0 ; pub const TIM_CCMR2_OC4M_ACTIVE : u32 = 4096 ; pub const TIM_CCMR2_OC4M_INACTIVE : u32 = 8192 ; pub const TIM_CCMR2_OC4M_TOGGLE : u32 = 12288 ; pub const TIM_CCMR2_OC4M_FORCE_LOW : u32 = 16384 ; pub const TIM_CCMR2_OC4M_FORCE_HIGH : u32 = 20480 ; pub const TIM_CCMR2_OC4M_PWM1 : u32 = 24576 ; pub const TIM_CCMR2_OC4M_PWM2 : u32 = 28672 ; pub const TIM_CCMR2_OC4M_MASK : u32 = 28672 ; pub const TIM_CCMR2_OC4PE : u32 = 2048 ; pub const TIM_CCMR2_OC4FE : u32 = 1024 ; pub const TIM_CCMR2_CC4S_OUT : u32 = 0 ; pub const TIM_CCMR2_CC4S_IN_TI4 : u32 = 256 ; pub const TIM_CCMR2_CC4S_IN_TI3 : u32 = 512 ; pub const TIM_CCMR2_CC4S_IN_TRC : u32 = 768 ; pub const TIM_CCMR2_CC4S_MASK : u32 = 768 ; pub const TIM_CCMR2_OC3CE : u32 = 128 ; pub const TIM_CCMR2_OC3M_FROZEN : u32 = 0 ; pub const TIM_CCMR2_OC3M_ACTIVE : u32 = 16 ; pub const TIM_CCMR2_OC3M_INACTIVE : u32 = 32 ; pub const TIM_CCMR2_OC3M_TOGGLE : u32 = 48 ; pub const TIM_CCMR2_OC3M_FORCE_LOW : u32 = 64 ; pub const TIM_CCMR2_OC3M_FORCE_HIGH : u32 = 80 ; pub const TIM_CCMR2_OC3M_PWM1 : u32 = 96 ; pub const TIM_CCMR2_OC3M_PWM2 : u32 = 112 ; pub const TIM_CCMR2_OC3M_MASK : u32 = 112 ; pub const TIM_CCMR2_OC3PE : u32 = 8 ; pub const TIM_CCMR2_OC3FE : u32 = 4 ; pub const TIM_CCMR2_CC3S_OUT : u32 = 0 ; pub const TIM_CCMR2_CC3S_IN_TI3 : u32 = 1 ; pub const TIM_CCMR2_CC3S_IN_TI4 : u32 = 2 ; pub const TIM_CCMR2_CC3S_IN_TRC : u32 = 3 ; pub const TIM_CCMR2_CC3S_MASK : u32 = 3 ; pub const TIM_CCMR2_IC4F_OFF : u32 = 0 ; pub const TIM_CCMR2_IC4F_CK_INT_N_2 : u32 = 4096 ; pub const TIM_CCMR2_IC4F_CK_INT_N_4 : u32 = 8192 ; pub const TIM_CCMR2_IC4F_CK_INT_N_8 : u32 = 12288 ; pub const TIM_CCMR2_IC4F_DTF_DIV_2_N_6 : u32 = 16384 ; pub const TIM_CCMR2_IC4F_DTF_DIV_2_N_8 : u32 = 20480 ; pub const TIM_CCMR2_IC4F_DTF_DIV_4_N_6 : u32 = 24576 ; pub const TIM_CCMR2_IC4F_DTF_DIV_4_N_8 : u32 = 28672 ; pub const TIM_CCMR2_IC4F_DTF_DIV_8_N_6 : u32 = 32768 ; pub const TIM_CCMR2_IC4F_DTF_DIV_8_N_8 : u32 = 36864 ; pub const TIM_CCMR2_IC4F_DTF_DIV_16_N_5 : u32 = 40960 ; pub const TIM_CCMR2_IC4F_DTF_DIV_16_N_6 : u32 = 45056 ; pub const TIM_CCMR2_IC4F_DTF_DIV_16_N_8 : u32 = 49152 ; pub const TIM_CCMR2_IC4F_DTF_DIV_32_N_5 : u32 = 53248 ; pub const TIM_CCMR2_IC4F_DTF_DIV_32_N_6 : u32 = 57344 ; pub const TIM_CCMR2_IC4F_DTF_DIV_32_N_8 : u32 = 61440 ; pub const TIM_CCMR2_IC4F_MASK : u32 = 61440 ; pub const TIM_CCMR2_IC4PSC_OFF : u32 = 0 ; pub const TIM_CCMR2_IC4PSC_2 : u32 = 1024 ; pub const TIM_CCMR2_IC4PSC_4 : u32 = 2048 ; pub const TIM_CCMR2_IC4PSC_8 : u32 = 3072 ; pub const TIM_CCMR2_IC4PSC_MASK : u32 = 3072 ; pub const TIM_CCMR2_IC3F_OFF : u32 = 0 ; pub const TIM_CCMR2_IC3F_CK_INT_N_2 : u32 = 16 ; pub const TIM_CCMR2_IC3F_CK_INT_N_4 : u32 = 32 ; pub const TIM_CCMR2_IC3F_CK_INT_N_8 : u32 = 48 ; pub const TIM_CCMR2_IC3F_DTF_DIV_2_N_6 : u32 = 64 ; pub const TIM_CCMR2_IC3F_DTF_DIV_2_N_8 : u32 = 80 ; pub const TIM_CCMR2_IC3F_DTF_DIV_4_N_6 : u32 = 96 ; pub const TIM_CCMR2_IC3F_DTF_DIV_4_N_8 : u32 = 112 ; pub const TIM_CCMR2_IC3F_DTF_DIV_8_N_6 : u32 = 128 ; pub const TIM_CCMR2_IC3F_DTF_DIV_8_N_8 : u32 = 144 ; pub const TIM_CCMR2_IC3F_DTF_DIV_16_N_5 : u32 = 160 ; pub const TIM_CCMR2_IC3F_DTF_DIV_16_N_6 : u32 = 176 ; pub const TIM_CCMR2_IC3F_DTF_DIV_16_N_8 : u32 = 192 ; pub const TIM_CCMR2_IC3F_DTF_DIV_32_N_5 : u32 = 208 ; pub const TIM_CCMR2_IC3F_DTF_DIV_32_N_6 : u32 = 224 ; pub const TIM_CCMR2_IC3F_DTF_DIV_32_N_8 : u32 = 240 ; pub const TIM_CCMR2_IC3F_MASK : u32 = 240 ; pub const TIM_CCMR2_IC3PSC_OFF : u32 = 0 ; pub const TIM_CCMR2_IC3PSC_2 : u32 = 4 ; pub const TIM_CCMR2_IC3PSC_4 : u32 = 8 ; pub const TIM_CCMR2_IC3PSC_8 : u32 = 12 ; pub const TIM_CCMR2_IC3PSC_MASK : u32 = 12 ; pub const TIM_CCER_CC4NP : u32 = 32768 ; pub const TIM_CCER_CC4P : u32 = 8192 ; pub const TIM_CCER_CC4E : u32 = 4096 ; pub const TIM_CCER_CC3NP : u32 = 2048 ; pub const TIM_CCER_CC3NE : u32 = 1024 ; pub const TIM_CCER_CC3P : u32 = 512 ; pub const TIM_CCER_CC3E : u32 = 256 ; pub const TIM_CCER_CC2NP : u32 = 128 ; pub const TIM_CCER_CC2NE : u32 = 64 ; pub const TIM_CCER_CC2P : u32 = 32 ; pub const TIM_CCER_CC2E : u32 = 16 ; pub const TIM_CCER_CC1NP : u32 = 8 ; pub const TIM_CCER_CC1NE : u32 = 4 ; pub const TIM_CCER_CC1P : u32 = 2 ; pub const TIM_CCER_CC1E : u32 = 1 ; pub const TIM_BDTR_MOE : u32 = 32768 ; pub const TIM_BDTR_AOE : u32 = 16384 ; pub const TIM_BDTR_BKP : u32 = 8192 ; pub const TIM_BDTR_BKE : u32 = 4096 ; pub const TIM_BDTR_OSSR : u32 = 2048 ; pub const TIM_BDTR_OSSI : u32 = 1024 ; pub const TIM_BDTR_LOCK_OFF : u32 = 0 ; pub const TIM_BDTR_LOCK_LEVEL_1 : u32 = 256 ; pub const TIM_BDTR_LOCK_LEVEL_2 : u32 = 512 ; pub const TIM_BDTR_LOCK_LEVEL_3 : u32 = 768 ; pub const TIM_BDTR_LOCK_MASK : u32 = 768 ; pub const TIM_BDTR_DTG_MASK : u32 = 255 ; pub const TIM_BDTR_DBL_MASK : u32 = 7936 ; pub const TIM_BDTR_DBA_MASK : u32 = 31 ; pub const USART_PARITY_NONE : u32 = 0 ; pub const USART_CR2_STOPBITS_1 : u32 = 0 ; pub const USART_CR2_STOPBITS_0_5 : u32 = 4096 ; pub const USART_CR2_STOPBITS_2 : u32 = 8192 ; pub const USART_CR2_STOPBITS_1_5 : u32 = 12288 ; pub const USART_CR2_STOPBITS_MASK : u32 = 12288 ; pub const USART_CR2_STOPBITS_SHIFT : u32 = 12 ; pub const USART_FLOWCONTROL_NONE : u32 = 0 ; pub const USART1 : u32 = 1073821696 ; pub const USART2 : u32 = 1073759232 ; pub const USART3 : u32 = 1073760256 ; pub const UART4 : u32 = 1073761280 ; pub const UART5 : u32 = 1073762304 ; pub const USART_SR_CTS : u32 = 512 ; pub const USART_SR_LBD : u32 = 256 ; pub const USART_SR_TXE : u32 = 128 ; pub const USART_SR_TC : u32 = 64 ; pub const USART_SR_RXNE : u32 = 32 ; pub const USART_SR_IDLE : u32 = 16 ; pub const USART_SR_ORE : u32 = 8 ; pub const USART_SR_NE : u32 = 4 ; pub const USART_SR_FE : u32 = 2 ; pub const USART_SR_PE : u32 = 1 ; pub const USART_DR_MASK : u32 = 511 ; pub const USART_BRR_DIV_MANTISSA_MASK : u32 = 65520 ; pub const USART_BRR_DIV_FRACTION_MASK : u32 = 15 ; pub const USART_CR1_UE : u32 = 8192 ; pub const USART_CR1_M : u32 = 4096 ; pub const USART_CR1_WAKE : u32 = 2048 ; pub const USART_CR1_PCE : u32 = 1024 ; pub const USART_CR1_PS : u32 = 512 ; pub const USART_CR1_PEIE : u32 = 256 ; pub const USART_CR1_TXEIE : u32 = 128 ; pub const USART_CR1_TCIE : u32 = 64 ; pub const USART_CR1_RXNEIE : u32 = 32 ; pub const USART_CR1_IDLEIE : u32 = 16 ; pub const USART_CR1_TE : u32 = 8 ; pub const USART_CR1_RE : u32 = 4 ; pub const USART_CR1_RWU : u32 = 2 ; pub const USART_CR1_SBK : u32 = 1 ; pub const USART_CR2_LINEN : u32 = 16384 ; pub const USART_CR2_CLKEN : u32 = 2048 ; pub const USART_CR2_CPOL : u32 = 1024 ; pub const USART_CR2_CPHA : u32 = 512 ; pub const USART_CR2_LBCL : u32 = 256 ; pub const USART_CR2_LBDIE : u32 = 64 ; pub const USART_CR2_LBDL : u32 = 32 ; pub const USART_CR2_ADD_MASK : u32 = 15 ; pub const USART_CR3_CTSIE : u32 = 1024 ; pub const USART_CR3_CTSE : u32 = 512 ; pub const USART_CR3_RTSE : u32 = 256 ; pub const USART_CR3_DMAT : u32 = 128 ; pub const USART_CR3_DMAR : u32 = 64 ; pub const USART_CR3_SCEN : u32 = 32 ; pub const USART_CR3_NACK : u32 = 16 ; pub const USART_CR3_HDSEL : u32 = 8 ; pub const USART_CR3_IRLP : u32 = 4 ; pub const USART_CR3_IREN : u32 = 2 ; pub const USART_CR3_EIE : u32 = 1 ; pub const USART_GTPR_GT_MASK : u32 = 65280 ; pub const USART_GTPR_PSC_MASK : u32 = 255 ; pub type int_least8_t = raw_c_types :: c_schar ; pub type int_least16_t = raw_c_types :: c_short ; pub type int_least32_t = raw_c_types :: c_int ; pub type int_least64_t = raw_c_types :: c_long ; pub type uint_least8_t = raw_c_types :: c_uchar ; pub type uint_least16_t = raw_c_types :: c_ushort ; pub type uint_least32_t = raw_c_types :: c_uint ; pub type uint_least64_t = raw_c_types :: c_ulong ; pub type int_fast8_t = raw_c_types :: c_schar ; pub type int_fast16_t = raw_c_types :: c_long ; pub type int_fast32_t = raw_c_types :: c_long ; pub type int_fast64_t = raw_c_types :: c_long ; pub type uint_fast8_t = raw_c_types :: c_uchar ; pub type uint_fast16_t = raw_c_types :: c_ulong ; pub type uint_fast32_t = raw_c_types :: c_ulong ; pub type uint_fast64_t = raw_c_types :: c_ulong ; pub type intmax_t = raw_c_types :: c_long ; pub type uintmax_t = raw_c_types :: c_ulong ; extern "C" { 
  
 pub fn dwt_enable_cycle_counter ( ) -> bool ; } extern "C" { pub fn dwt_read_cycle_counter ( ) -> u32 ; } extern "C" { 
 /// @defgroup CM3_nvic_isrprototypes_STM32F1 User interrupt service routines (ISR) prototypes for STM32 F1 series
/// @ingroup CM3_nvic_isrprototypes
///
/// @{ 
 pub fn wwdg_isr ( ) ; } extern "C" { pub fn pvd_isr ( ) ; } extern "C" { pub fn tamper_isr ( ) ; } extern "C" { pub fn rtc_isr ( ) ; } extern "C" { pub fn flash_isr ( ) ; } extern "C" { pub fn rcc_isr ( ) ; } extern "C" { pub fn exti0_isr ( ) ; } extern "C" { pub fn exti1_isr ( ) ; } extern "C" { pub fn exti2_isr ( ) ; } extern "C" { pub fn exti3_isr ( ) ; } extern "C" { pub fn exti4_isr ( ) ; } extern "C" { pub fn dma1_channel1_isr ( ) ; } extern "C" { pub fn dma1_channel2_isr ( ) ; } extern "C" { pub fn dma1_channel3_isr ( ) ; } extern "C" { pub fn dma1_channel4_isr ( ) ; } extern "C" { pub fn dma1_channel5_isr ( ) ; } extern "C" { pub fn dma1_channel6_isr ( ) ; } extern "C" { pub fn dma1_channel7_isr ( ) ; } extern "C" { pub fn adc1_2_isr ( ) ; } extern "C" { pub fn usb_hp_can_tx_isr ( ) ; } extern "C" { pub fn usb_lp_can_rx0_isr ( ) ; } extern "C" { pub fn can_rx1_isr ( ) ; } extern "C" { pub fn can_sce_isr ( ) ; } extern "C" { pub fn exti9_5_isr ( ) ; } extern "C" { pub fn tim1_brk_isr ( ) ; } extern "C" { pub fn tim1_up_isr ( ) ; } extern "C" { pub fn tim1_trg_com_isr ( ) ; } extern "C" { pub fn tim1_cc_isr ( ) ; } extern "C" { pub fn tim2_isr ( ) ; } extern "C" { pub fn tim3_isr ( ) ; } extern "C" { pub fn tim4_isr ( ) ; } extern "C" { pub fn i2c1_ev_isr ( ) ; } extern "C" { pub fn i2c1_er_isr ( ) ; } extern "C" { pub fn i2c2_ev_isr ( ) ; } extern "C" { pub fn i2c2_er_isr ( ) ; } extern "C" { pub fn spi1_isr ( ) ; } extern "C" { pub fn spi2_isr ( ) ; } extern "C" { pub fn usart1_isr ( ) ; } extern "C" { pub fn usart2_isr ( ) ; } extern "C" { pub fn usart3_isr ( ) ; } extern "C" { pub fn exti15_10_isr ( ) ; } extern "C" { pub fn rtc_alarm_isr ( ) ; } extern "C" { pub fn usb_wakeup_isr ( ) ; } extern "C" { pub fn tim8_brk_isr ( ) ; } extern "C" { pub fn tim8_up_isr ( ) ; } extern "C" { pub fn tim8_trg_com_isr ( ) ; } extern "C" { pub fn tim8_cc_isr ( ) ; } extern "C" { pub fn adc3_isr ( ) ; } extern "C" { pub fn fsmc_isr ( ) ; } extern "C" { pub fn sdio_isr ( ) ; } extern "C" { pub fn tim5_isr ( ) ; } extern "C" { pub fn spi3_isr ( ) ; } extern "C" { pub fn uart4_isr ( ) ; } extern "C" { pub fn uart5_isr ( ) ; } extern "C" { pub fn tim6_isr ( ) ; } extern "C" { pub fn tim7_isr ( ) ; } extern "C" { pub fn dma2_channel1_isr ( ) ; } extern "C" { pub fn dma2_channel2_isr ( ) ; } extern "C" { pub fn dma2_channel3_isr ( ) ; } extern "C" { pub fn dma2_channel4_5_isr ( ) ; } extern "C" { pub fn dma2_channel5_isr ( ) ; } extern "C" { pub fn eth_isr ( ) ; } extern "C" { pub fn eth_wkup_isr ( ) ; } extern "C" { pub fn can2_tx_isr ( ) ; } extern "C" { pub fn can2_rx0_isr ( ) ; } extern "C" { pub fn can2_rx1_isr ( ) ; } extern "C" { pub fn can2_sce_isr ( ) ; } extern "C" { pub fn otg_fs_isr ( ) ; } extern "C" { pub fn nvic_enable_irq ( irqn : u8 ) ; } extern "C" { pub fn nvic_disable_irq ( irqn : u8 ) ; } extern "C" { pub fn nvic_get_pending_irq ( irqn : u8 ) -> u8 ; } extern "C" { pub fn nvic_set_pending_irq ( irqn : u8 ) ; } extern "C" { pub fn nvic_clear_pending_irq ( irqn : u8 ) ; } extern "C" { pub fn nvic_get_irq_enabled ( irqn : u8 ) -> u8 ; } extern "C" { pub fn nvic_set_priority ( irqn : u8 , priority : u8 ) ; } extern "C" { pub fn reset_handler ( ) ; } extern "C" { pub fn nmi_handler ( ) ; } extern "C" { pub fn hard_fault_handler ( ) ; } extern "C" { pub fn sv_call_handler ( ) ; } extern "C" { pub fn pend_sv_handler ( ) ; } extern "C" { pub fn sys_tick_handler ( ) ; } # [ repr ( C , packed ) ] # [ derive ( Debug , Copy , Clone ) ] pub struct scb_exception_stack_frame { pub r0 : u32 , pub r1 : u32 , pub r2 : u32 , pub r3 : u32 , pub r12 : u32 , pub lr : u32 , pub pc : u32 , pub xpsr : u32 , } # [ test ] fn bindgen_test_layout_scb_exception_stack_frame ( ) { assert_eq ! ( :: core :: mem :: size_of :: < scb_exception_stack_frame > ( ) , 32usize , concat ! ( "Size of: " , stringify ! ( scb_exception_stack_frame ) ) ) ; assert_eq ! ( :: core :: mem :: align_of :: < scb_exception_stack_frame > ( ) , 1usize , concat ! ( "Alignment of " , stringify ! ( scb_exception_stack_frame ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < scb_exception_stack_frame > ( ) ) ) . r0 as * const _ as usize } , 0usize , concat ! ( "Offset of field: " , stringify ! ( scb_exception_stack_frame ) , "::" , stringify ! ( r0 ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < scb_exception_stack_frame > ( ) ) ) . r1 as * const _ as usize } , 4usize , concat ! ( "Offset of field: " , stringify ! ( scb_exception_stack_frame ) , "::" , stringify ! ( r1 ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < scb_exception_stack_frame > ( ) ) ) . r2 as * const _ as usize } , 8usize , concat ! ( "Offset of field: " , stringify ! ( scb_exception_stack_frame ) , "::" , stringify ! ( r2 ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < scb_exception_stack_frame > ( ) ) ) . r3 as * const _ as usize } , 12usize , concat ! ( "Offset of field: " , stringify ! ( scb_exception_stack_frame ) , "::" , stringify ! ( r3 ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < scb_exception_stack_frame > ( ) ) ) . r12 as * const _ as usize } , 16usize , concat ! ( "Offset of field: " , stringify ! ( scb_exception_stack_frame ) , "::" , stringify ! ( r12 ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < scb_exception_stack_frame > ( ) ) ) . lr as * const _ as usize } , 20usize , concat ! ( "Offset of field: " , stringify ! ( scb_exception_stack_frame ) , "::" , stringify ! ( lr ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < scb_exception_stack_frame > ( ) ) ) . pc as * const _ as usize } , 24usize , concat ! ( "Offset of field: " , stringify ! ( scb_exception_stack_frame ) , "::" , stringify ! ( pc ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < scb_exception_stack_frame > ( ) ) ) . xpsr as * const _ as usize } , 28usize , concat ! ( "Offset of field: " , stringify ! ( scb_exception_stack_frame ) , "::" , stringify ! ( xpsr ) ) ) ; } extern "C" { pub fn scb_reset_system ( ) ; } extern "C" { pub fn __dmb ( ) ; } extern "C" { pub fn systick_set_reload ( value : u32 ) ; } extern "C" { pub fn systick_set_frequency ( freq : u32 , ahb : u32 ) -> bool ; } extern "C" { pub fn systick_get_reload ( ) -> u32 ; } extern "C" { pub fn systick_get_value ( ) -> u32 ; } extern "C" { pub fn systick_set_clocksource ( clocksource : u8 ) ; } extern "C" { pub fn systick_interrupt_enable ( ) ; } extern "C" { pub fn systick_interrupt_disable ( ) ; } extern "C" { pub fn systick_counter_enable ( ) ; } extern "C" { pub fn systick_counter_disable ( ) ; } extern "C" { pub fn systick_get_countflag ( ) -> u8 ; } extern "C" { pub fn systick_clear ( ) ; } extern "C" { pub fn systick_get_calib ( ) -> u32 ; } 
 /// Type of an interrupt function. Only used to avoid hard-to-read function
/// pointers in the efm32_vector_table_t struct. 
 pub type vector_table_entry_t = :: core :: option :: Option < unsafe extern "C" fn ( ) > ; # [ repr ( C ) ] # [ derive ( Copy , Clone ) ] pub struct vector_table_t { 
 /// < Initial stack pointer value. 
 pub initial_sp_value : * mut raw_c_types :: c_uint , pub reset : vector_table_entry_t , pub nmi : vector_table_entry_t , pub hard_fault : vector_table_entry_t , pub memory_manage_fault : vector_table_entry_t , pub bus_fault : vector_table_entry_t , pub usage_fault : vector_table_entry_t , pub reserved_x001c : [ vector_table_entry_t ; 4usize ] , pub sv_call : vector_table_entry_t , pub debug_monitor : vector_table_entry_t , pub reserved_x0034 : vector_table_entry_t , pub pend_sv : vector_table_entry_t , pub systick : vector_table_entry_t , pub irq : [ vector_table_entry_t ; 68usize ] , } # [ test ] fn bindgen_test_layout_vector_table_t ( ) { assert_eq ! ( :: core :: mem :: size_of :: < vector_table_t > ( ) , 672usize , concat ! ( "Size of: " , stringify ! ( vector_table_t ) ) ) ; assert_eq ! ( :: core :: mem :: align_of :: < vector_table_t > ( ) , 8usize , concat ! ( "Alignment of " , stringify ! ( vector_table_t ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . initial_sp_value as * const _ as usize } , 0usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( initial_sp_value ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . reset as * const _ as usize } , 8usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( reset ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . nmi as * const _ as usize } , 16usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( nmi ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . hard_fault as * const _ as usize } , 24usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( hard_fault ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . memory_manage_fault as * const _ as usize } , 32usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( memory_manage_fault ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . bus_fault as * const _ as usize } , 40usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( bus_fault ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . usage_fault as * const _ as usize } , 48usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( usage_fault ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . reserved_x001c as * const _ as usize } , 56usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( reserved_x001c ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . sv_call as * const _ as usize } , 88usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( sv_call ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . debug_monitor as * const _ as usize } , 96usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( debug_monitor ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . reserved_x0034 as * const _ as usize } , 104usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( reserved_x0034 ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . pend_sv as * const _ as usize } , 112usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( pend_sv ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . systick as * const _ as usize } , 120usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( systick ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < vector_table_t > ( ) ) ) . irq as * const _ as usize } , 128usize , concat ! ( "Offset of field: " , stringify ! ( vector_table_t ) , "::" , stringify ! ( irq ) ) ) ; } extern "C" { # [ link_name = "\u{1}_data_loadaddr" ] pub static mut _data_loadaddr : raw_c_types :: c_uint ; } extern "C" { # [ link_name = "\u{1}_data" ] pub static mut _data : raw_c_types :: c_uint ; } extern "C" { # [ link_name = "\u{1}_edata" ] pub static mut _edata : raw_c_types :: c_uint ; } extern "C" { # [ link_name = "\u{1}_ebss" ] pub static mut _ebss : raw_c_types :: c_uint ; } extern "C" { # [ link_name = "\u{1}_stack" ] pub static mut _stack : raw_c_types :: c_uint ; } extern "C" { # [ link_name = "\u{1}vector_table" ] pub static mut vector_table : vector_table_t ; } extern "C" { pub fn adc_power_on ( adc : u32 ) ; } extern "C" { pub fn adc_power_off ( adc : u32 ) ; } extern "C" { pub fn adc_enable_analog_watchdog_regular ( adc : u32 ) ; } extern "C" { pub fn adc_disable_analog_watchdog_regular ( adc : u32 ) ; } extern "C" { pub fn adc_enable_analog_watchdog_injected ( adc : u32 ) ; } extern "C" { pub fn adc_disable_analog_watchdog_injected ( adc : u32 ) ; } extern "C" { pub fn adc_enable_discontinuous_mode_regular ( adc : u32 , length : u8 ) ; } extern "C" { pub fn adc_disable_discontinuous_mode_regular ( adc : u32 ) ; } extern "C" { pub fn adc_enable_discontinuous_mode_injected ( adc : u32 ) ; } extern "C" { pub fn adc_disable_discontinuous_mode_injected ( adc : u32 ) ; } extern "C" { pub fn adc_enable_automatic_injected_group_conversion ( adc : u32 ) ; } extern "C" { pub fn adc_disable_automatic_injected_group_conversion ( adc : u32 ) ; } extern "C" { pub fn adc_enable_analog_watchdog_on_all_channels ( adc : u32 ) ; } extern "C" { pub fn adc_enable_analog_watchdog_on_selected_channel ( adc : u32 , channel : u8 ) ; } extern "C" { pub fn adc_enable_scan_mode ( adc : u32 ) ; } extern "C" { pub fn adc_disable_scan_mode ( adc : u32 ) ; } extern "C" { pub fn adc_enable_eoc_interrupt_injected ( adc : u32 ) ; } extern "C" { pub fn adc_disable_eoc_interrupt_injected ( adc : u32 ) ; } extern "C" { pub fn adc_enable_awd_interrupt ( adc : u32 ) ; } extern "C" { pub fn adc_disable_awd_interrupt ( adc : u32 ) ; } extern "C" { pub fn adc_enable_eoc_interrupt ( adc : u32 ) ; } extern "C" { pub fn adc_disable_eoc_interrupt ( adc : u32 ) ; } extern "C" { pub fn adc_set_left_aligned ( adc : u32 ) ; } extern "C" { pub fn adc_set_right_aligned ( adc : u32 ) ; } extern "C" { pub fn adc_eoc ( adc : u32 ) -> bool ; } extern "C" { pub fn adc_eoc_injected ( adc : u32 ) -> bool ; } extern "C" { pub fn adc_read_regular ( adc : u32 ) -> u32 ; } extern "C" { pub fn adc_read_injected ( adc : u32 , reg : u8 ) -> u32 ; } extern "C" { pub fn adc_set_continuous_conversion_mode ( adc : u32 ) ; } extern "C" { pub fn adc_set_single_conversion_mode ( adc : u32 ) ; } extern "C" { pub fn adc_set_regular_sequence ( adc : u32 , length : u8 , channel : * mut u8 ) ; } extern "C" { pub fn adc_set_injected_sequence ( adc : u32 , length : u8 , channel : * mut u8 ) ; } extern "C" { pub fn adc_set_injected_offset ( adc : u32 , reg : u8 , offset : u32 ) ; } extern "C" { pub fn adc_set_watchdog_high_threshold ( adc : u32 , threshold : u16 ) ; } extern "C" { pub fn adc_set_watchdog_low_threshold ( adc : u32 , threshold : u16 ) ; } extern "C" { pub fn adc_start_conversion_regular ( adc : u32 ) ; } extern "C" { pub fn adc_start_conversion_injected ( adc : u32 ) ; } extern "C" { pub fn adc_enable_dma ( adc : u32 ) ; } extern "C" { pub fn adc_disable_dma ( adc : u32 ) ; } extern "C" { pub fn adc_set_sample_time ( adc : u32 , channel : u8 , time : u8 ) ; } extern "C" { pub fn adc_set_sample_time_on_all_channels ( adc : u32 , time : u8 ) ; } extern "C" { pub fn adc_disable_external_trigger_regular ( adc : u32 ) ; } extern "C" { pub fn adc_disable_external_trigger_injected ( adc : u32 ) ; } extern "C" { 
 /// @} 
 pub fn adc_start_conversion_direct ( adc : u32 ) ; } extern "C" { pub fn adc_set_dual_mode ( mode : u32 ) ; } extern "C" { pub fn adc_enable_temperature_sensor ( ) ; } extern "C" { pub fn adc_disable_temperature_sensor ( ) ; } extern "C" { pub fn adc_enable_external_trigger_regular ( adc : u32 , trigger : u32 ) ; } extern "C" { pub fn adc_enable_external_trigger_injected ( adc : u32 , trigger : u32 ) ; } extern "C" { pub fn adc_reset_calibration ( adc : u32 ) ; } extern "C" { pub fn adc_calibration ( adc : u32 ) ; } extern "C" { pub fn adc_calibrate_async ( adc : u32 ) ; } extern "C" { pub fn adc_is_calibrating ( adc : u32 ) -> bool ; } extern "C" { pub fn adc_calibrate ( adc : u32 ) ; } extern "C" { pub fn can_reset ( canport : u32 ) ; } extern "C" { pub fn can_init ( canport : u32 , ttcm : bool , abom : bool , awum : bool , nart : bool , rflm : bool , txfp : bool , sjw : u32 , ts1 : u32 , ts2 : u32 , brp : u32 , loopback : bool , silent : bool ) -> raw_c_types :: c_int ; } extern "C" { pub fn can_filter_init ( nr : u32 , scale_32bit : bool , id_list_mode : bool , fr1 : u32 , fr2 : u32 , fifo : u32 , enable : bool ) ; } extern "C" { pub fn can_filter_id_mask_16bit_init ( nr : u32 , id1 : u16 , mask1 : u16 , id2 : u16 , mask2 : u16 , fifo : u32 , enable : bool ) ; } extern "C" { pub fn can_filter_id_mask_32bit_init ( nr : u32 , id : u32 , mask : u32 , fifo : u32 , enable : bool ) ; } extern "C" { pub fn can_filter_id_list_16bit_init ( nr : u32 , id1 : u16 , id2 : u16 , id3 : u16 , id4 : u16 , fifo : u32 , enable : bool ) ; } extern "C" { pub fn can_filter_id_list_32bit_init ( nr : u32 , id1 : u32 , id2 : u32 , fifo : u32 , enable : bool ) ; } extern "C" { pub fn can_enable_irq ( canport : u32 , irq : u32 ) ; } extern "C" { pub fn can_disable_irq ( canport : u32 , irq : u32 ) ; } extern "C" { pub fn can_transmit ( canport : u32 , id : u32 , ext : bool , rtr : bool , length : u8 , data : * mut u8 ) -> raw_c_types :: c_int ; } extern "C" { pub fn can_receive ( canport : u32 , fifo : u8 , release : bool , id : * mut u32 , ext : * mut bool , rtr : * mut bool , fmi : * mut u8 , length : * mut u8 , data : * mut u8 , timestamp : * mut u16 ) ; } extern "C" { pub fn can_fifo_release ( canport : u32 , fifo : u8 ) ; } extern "C" { pub fn can_available_mailbox ( canport : u32 ) -> bool ; } extern "C" { 
 /// Reset the CRC calculator to initial values. 
 pub fn crc_reset ( ) ; } extern "C" { 
 /// Add a word to the CRC calculator and return the result.
/// @param data new word to add to the CRC calculator
/// @return final CRC calculator value 
 pub fn crc_calculate ( data : u32 ) -> u32 ; } extern "C" { 
 /// Add a block of data to the CRC calculator and return the final result
/// @param datap pointer to the start of a block of 32bit data words
/// @param size length of data, in 32bit increments
/// @return final CRC calculator value 
 pub fn crc_calculate_block ( datap : * mut u32 , size : raw_c_types :: c_int ) -> u32 ; } pub const data_channel_CHANNEL_1 : data_channel = 0 ; pub const data_channel_CHANNEL_2 : data_channel = 1 ; pub const data_channel_CHANNEL_D : data_channel = 2 ; 
 /// DAC channel identifier 
 pub type data_channel = u32 ; pub const data_align_RIGHT8 : data_align = 0 ; pub const data_align_RIGHT12 : data_align = 1 ; pub const data_align_LEFT12 : data_align = 2 ; 
 /// DAC data size (8/12 bits), alignment (right/left) 
 pub type data_align = u32 ; extern "C" { pub fn dac_enable ( dac_channel : data_channel ) ; } extern "C" { pub fn dac_disable ( dac_channel : data_channel ) ; } extern "C" { pub fn dac_buffer_enable ( dac_channel : data_channel ) ; } extern "C" { pub fn dac_buffer_disable ( dac_channel : data_channel ) ; } extern "C" { pub fn dac_dma_enable ( dac_channel : data_channel ) ; } extern "C" { pub fn dac_dma_disable ( dac_channel : data_channel ) ; } extern "C" { pub fn dac_trigger_enable ( dac_channel : data_channel ) ; } extern "C" { pub fn dac_trigger_disable ( dac_channel : data_channel ) ; } extern "C" { pub fn dac_set_trigger_source ( dac_trig_src : u32 ) ; } extern "C" { pub fn dac_set_waveform_generation ( dac_wave_ens : u32 ) ; } extern "C" { pub fn dac_disable_waveform_generation ( dac_channel : data_channel ) ; } extern "C" { pub fn dac_set_waveform_characteristics ( dac_mamp : u32 ) ; } extern "C" { pub fn dac_load_data_buffer_single ( dac_data : u16 , dac_data_format : data_align , dac_channel : data_channel ) ; } extern "C" { pub fn dac_load_data_buffer_dual ( dac_data1 : u16 , dac_data2 : u16 , dac_data_format : data_align ) ; } extern "C" { pub fn dac_software_trigger ( dac_channel : data_channel ) ; } extern "C" { 
 /// @} 
 pub fn dma_channel_reset ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_clear_interrupt_flags ( dma : u32 , channel : u8 , interrupts : u32 ) ; } extern "C" { pub fn dma_get_interrupt_flag ( dma : u32 , channel : u8 , interrupts : u32 ) -> bool ; } extern "C" { pub fn dma_enable_mem2mem_mode ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_set_priority ( dma : u32 , channel : u8 , prio : u32 ) ; } extern "C" { pub fn dma_set_memory_size ( dma : u32 , channel : u8 , mem_size : u32 ) ; } extern "C" { pub fn dma_set_peripheral_size ( dma : u32 , channel : u8 , peripheral_size : u32 ) ; } extern "C" { pub fn dma_enable_memory_increment_mode ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_disable_memory_increment_mode ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_enable_peripheral_increment_mode ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_disable_peripheral_increment_mode ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_enable_circular_mode ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_set_read_from_peripheral ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_set_read_from_memory ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_enable_transfer_error_interrupt ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_disable_transfer_error_interrupt ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_enable_half_transfer_interrupt ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_disable_half_transfer_interrupt ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_enable_transfer_complete_interrupt ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_disable_transfer_complete_interrupt ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_enable_channel ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_disable_channel ( dma : u32 , channel : u8 ) ; } extern "C" { pub fn dma_set_peripheral_address ( dma : u32 , channel : u8 , address : u32 ) ; } extern "C" { pub fn dma_set_memory_address ( dma : u32 , channel : u8 , address : u32 ) ; } extern "C" { pub fn dma_set_number_of_data ( dma : u32 , channel : u8 , number : u16 ) ; } pub const exti_trigger_type_EXTI_TRIGGER_RISING : exti_trigger_type = 0 ; pub const exti_trigger_type_EXTI_TRIGGER_FALLING : exti_trigger_type = 1 ; pub const exti_trigger_type_EXTI_TRIGGER_BOTH : exti_trigger_type = 2 ; pub type exti_trigger_type = u32 ; extern "C" { pub fn exti_set_trigger ( extis : u32 , trig : exti_trigger_type ) ; } extern "C" { pub fn exti_enable_request ( extis : u32 ) ; } extern "C" { pub fn exti_disable_request ( extis : u32 ) ; } extern "C" { pub fn exti_reset_request ( extis : u32 ) ; } extern "C" { pub fn exti_select_source ( exti : u32 , gpioport : u32 ) ; } extern "C" { pub fn exti_get_flag_status ( exti : u32 ) -> u32 ; } extern "C" { pub fn flash_set_ws ( ws : u32 ) ; } extern "C" { pub fn flash_prefetch_enable ( ) ; } extern "C" { pub fn flash_prefetch_disable ( ) ; } extern "C" { pub fn flash_unlock ( ) ; } extern "C" { pub fn flash_lock ( ) ; } extern "C" { pub fn flash_clear_pgerr_flag ( ) ; } extern "C" { pub fn flash_clear_eop_flag ( ) ; } extern "C" { pub fn flash_clear_wrprterr_flag ( ) ; } extern "C" { pub fn flash_clear_bsy_flag ( ) ; } extern "C" { pub fn flash_clear_status_flags ( ) ; } extern "C" { pub fn flash_get_status_flags ( ) -> u32 ; } extern "C" { pub fn flash_wait_for_last_operation ( ) ; } extern "C" { pub fn flash_program_word ( address : u32 , data : u32 ) ; } extern "C" { pub fn flash_program_half_word ( address : u32 , data : u16 ) ; } extern "C" { pub fn flash_erase_page ( page_address : u32 ) ; } extern "C" { pub fn flash_erase_all_pages ( ) ; } extern "C" { pub fn flash_unlock_option_bytes ( ) ; } extern "C" { pub fn flash_erase_option_bytes ( ) ; } extern "C" { pub fn flash_program_option_bytes ( address : u32 , data : u16 ) ; } extern "C" { pub fn flash_halfcycle_enable ( ) ; } extern "C" { pub fn flash_halfcycle_disable ( ) ; } extern "C" { pub fn flash_unlock_upper ( ) ; } extern "C" { pub fn flash_lock_upper ( ) ; } extern "C" { pub fn flash_clear_pgerr_flag_upper ( ) ; } extern "C" { pub fn flash_clear_eop_flag_upper ( ) ; } extern "C" { pub fn flash_clear_wrprterr_flag_upper ( ) ; } extern "C" { pub fn flash_clear_bsy_flag_upper ( ) ; } extern "C" { 
 /// @} 
 pub fn gpio_set ( gpioport : u32 , gpios : u16 ) ; } extern "C" { pub fn gpio_clear ( gpioport : u32 , gpios : u16 ) ; } extern "C" { pub fn gpio_get ( gpioport : u32 , gpios : u16 ) -> u16 ; } extern "C" { pub fn gpio_toggle ( gpioport : u32 , gpios : u16 ) ; } extern "C" { pub fn gpio_port_read ( gpioport : u32 ) -> u16 ; } extern "C" { pub fn gpio_port_write ( gpioport : u32 , data : u16 ) ; } extern "C" { pub fn gpio_port_config_lock ( gpioport : u32 , gpios : u16 ) ; } extern "C" { 
 /// @} 
 pub fn gpio_set_mode ( gpioport : u32 , mode : u8 , cnf : u8 , gpios : u16 ) ; } extern "C" { pub fn gpio_set_eventout ( evoutport : u8 , evoutpin : u8 ) ; } extern "C" { pub fn gpio_primary_remap ( swjenable : u32 , maps : u32 ) ; } extern "C" { pub fn gpio_secondary_remap ( maps : u32 ) ; } pub type wchar_t = raw_c_types :: c_int ; # [ repr ( C ) ] # [ derive ( Debug , Copy , Clone ) ] pub struct max_align_t { pub __clang_max_align_nonce1 : raw_c_types :: c_longlong , pub __bindgen_padding_0 : u64 , pub __clang_max_align_nonce2 : f64 , } # [ test ] fn bindgen_test_layout_max_align_t ( ) { assert_eq ! ( :: core :: mem :: size_of :: < max_align_t > ( ) , 32usize , concat ! ( "Size of: " , stringify ! ( max_align_t ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < max_align_t > ( ) ) ) . __clang_max_align_nonce1 as * const _ as usize } , 0usize , concat ! ( "Offset of field: " , stringify ! ( max_align_t ) , "::" , stringify ! ( __clang_max_align_nonce1 ) ) ) ; assert_eq ! ( unsafe { & ( * ( :: core :: ptr :: null :: < max_align_t > ( ) ) ) . __clang_max_align_nonce2 as * const _ as usize } , 16usize , concat ! ( "Offset of field: " , stringify ! ( max_align_t ) , "::" , stringify ! ( __clang_max_align_nonce2 ) ) ) ; } pub const i2c_speeds_i2c_speed_sm_100k : i2c_speeds = 0 ; pub const i2c_speeds_i2c_speed_fm_400k : i2c_speeds = 1 ; pub const i2c_speeds_i2c_speed_fmp_1m : i2c_speeds = 2 ; pub const i2c_speeds_i2c_speed_unknown : i2c_speeds = 3 ; 
 /// I2C speed modes. 
 pub type i2c_speeds = u32 ; extern "C" { pub fn i2c_reset ( i2c : u32 ) ; } extern "C" { pub fn i2c_peripheral_enable ( i2c : u32 ) ; } extern "C" { pub fn i2c_peripheral_disable ( i2c : u32 ) ; } extern "C" { pub fn i2c_send_start ( i2c : u32 ) ; } extern "C" { pub fn i2c_send_stop ( i2c : u32 ) ; } extern "C" { pub fn i2c_clear_stop ( i2c : u32 ) ; } extern "C" { pub fn i2c_set_own_7bit_slave_address ( i2c : u32 , slave : u8 ) ; } extern "C" { pub fn i2c_set_own_10bit_slave_address ( i2c : u32 , slave : u16 ) ; } extern "C" { pub fn i2c_set_own_7bit_slave_address_two ( i2c : u32 , slave : u8 ) ; } extern "C" { pub fn i2c_enable_dual_addressing_mode ( i2c : u32 ) ; } extern "C" { pub fn i2c_disable_dual_addressing_mode ( i2c : u32 ) ; } extern "C" { pub fn i2c_set_clock_frequency ( i2c : u32 , freq : u8 ) ; } extern "C" { pub fn i2c_send_data ( i2c : u32 , data : u8 ) ; } extern "C" { pub fn i2c_set_fast_mode ( i2c : u32 ) ; } extern "C" { pub fn i2c_set_standard_mode ( i2c : u32 ) ; } extern "C" { pub fn i2c_set_ccr ( i2c : u32 , freq : u16 ) ; } extern "C" { pub fn i2c_set_trise ( i2c : u32 , trise : u16 ) ; } extern "C" { pub fn i2c_send_7bit_address ( i2c : u32 , slave : u8 , readwrite : u8 ) ; } extern "C" { pub fn i2c_get_data ( i2c : u32 ) -> u8 ; } extern "C" { pub fn i2c_enable_interrupt ( i2c : u32 , interrupt : u32 ) ; } extern "C" { pub fn i2c_disable_interrupt ( i2c : u32 , interrupt : u32 ) ; } extern "C" { pub fn i2c_enable_ack ( i2c : u32 ) ; } extern "C" { pub fn i2c_disable_ack ( i2c : u32 ) ; } extern "C" { pub fn i2c_nack_next ( i2c : u32 ) ; } extern "C" { pub fn i2c_nack_current ( i2c : u32 ) ; } extern "C" { pub fn i2c_set_dutycycle ( i2c : u32 , dutycycle : u32 ) ; } extern "C" { pub fn i2c_enable_dma ( i2c : u32 ) ; } extern "C" { pub fn i2c_disable_dma ( i2c : u32 ) ; } extern "C" { pub fn i2c_set_dma_last_transfer ( i2c : u32 ) ; } extern "C" { pub fn i2c_clear_dma_last_transfer ( i2c : u32 ) ; } extern "C" { pub fn i2c_transfer7 ( i2c : u32 , addr : u8 , w : * mut u8 , wn : usize , r : * mut u8 , rn : usize ) ; } extern "C" { pub fn i2c_set_speed ( i2c : u32 , speed : i2c_speeds , clock_megahz : u32 ) ; } extern "C" { pub fn iwdg_start ( ) ; } extern "C" { pub fn iwdg_set_period_ms ( period : u32 ) ; } extern "C" { pub fn iwdg_reload_busy ( ) -> bool ; } extern "C" { pub fn iwdg_prescaler_busy ( ) -> bool ; } extern "C" { pub fn iwdg_reset ( ) ; } extern "C" { pub fn pwr_disable_backup_domain_write_protect ( ) ; } extern "C" { pub fn pwr_enable_backup_domain_write_protect ( ) ; } extern "C" { pub fn pwr_enable_power_voltage_detect ( pvd_level : u32 ) ; } extern "C" { pub fn pwr_disable_power_voltage_detect ( ) ; } extern "C" { pub fn pwr_clear_standby_flag ( ) ; } extern "C" { pub fn pwr_clear_wakeup_flag ( ) ; } extern "C" { pub fn pwr_set_standby_mode ( ) ; } extern "C" { pub fn pwr_set_stop_mode ( ) ; } extern "C" { pub fn pwr_voltage_regulator_on_in_stop ( ) ; } extern "C" { pub fn pwr_voltage_regulator_low_power_in_stop ( ) ; } extern "C" { pub fn pwr_enable_wakeup_pin ( ) ; } extern "C" { pub fn pwr_disable_wakeup_pin ( ) ; } extern "C" { pub fn pwr_voltage_high ( ) -> bool ; } extern "C" { pub fn pwr_get_standby_flag ( ) -> bool ; } extern "C" { pub fn pwr_get_wakeup_flag ( ) -> bool ; } extern "C" { # [ link_name = "\u{1}rcc_ahb_frequency" ] pub static mut rcc_ahb_frequency : u32 ; } extern "C" { # [ link_name = "\u{1}rcc_apb1_frequency" ] pub static mut rcc_apb1_frequency : u32 ; } extern "C" { # [ link_name = "\u{1}rcc_apb2_frequency" ] pub static mut rcc_apb2_frequency : u32 ; } pub const rcc_osc_RCC_PLL : rcc_osc = 0 ; pub const rcc_osc_RCC_PLL2 : rcc_osc = 1 ; pub const rcc_osc_RCC_PLL3 : rcc_osc = 2 ; pub const rcc_osc_RCC_HSE : rcc_osc = 3 ; pub const rcc_osc_RCC_HSI : rcc_osc = 4 ; pub const rcc_osc_RCC_LSE : rcc_osc = 5 ; pub const rcc_osc_RCC_LSI : rcc_osc = 6 ; pub type rcc_osc = u32 ; pub const rcc_periph_clken_RCC_DMA1 : rcc_periph_clken = 640 ; pub const rcc_periph_clken_RCC_DMA2 : rcc_periph_clken = 641 ; pub const rcc_periph_clken_RCC_SRAM : rcc_periph_clken = 642 ; pub const rcc_periph_clken_RCC_FLTF : rcc_periph_clken = 644 ; pub const rcc_periph_clken_RCC_CRC : rcc_periph_clken = 646 ; pub const rcc_periph_clken_RCC_FSMC : rcc_periph_clken = 648 ; pub const rcc_periph_clken_RCC_SDIO : rcc_periph_clken = 650 ; pub const rcc_periph_clken_RCC_OTGFS : rcc_periph_clken = 652 ; pub const rcc_periph_clken_RCC_ETHMAC : rcc_periph_clken = 654 ; pub const rcc_periph_clken_RCC_ETHMACTX : rcc_periph_clken = 655 ; pub const rcc_periph_clken_RCC_ETHMACRX : rcc_periph_clken = 656 ; pub const rcc_periph_clken_RCC_AFIO : rcc_periph_clken = 768 ; pub const rcc_periph_clken_RCC_GPIOA : rcc_periph_clken = 770 ; pub const rcc_periph_clken_RCC_GPIOB : rcc_periph_clken = 771 ; pub const rcc_periph_clken_RCC_GPIOC : rcc_periph_clken = 772 ; pub const rcc_periph_clken_RCC_GPIOD : rcc_periph_clken = 773 ; pub const rcc_periph_clken_RCC_GPIOE : rcc_periph_clken = 774 ; pub const rcc_periph_clken_RCC_GPIOF : rcc_periph_clken = 775 ; pub const rcc_periph_clken_RCC_GPIOG : rcc_periph_clken = 776 ; pub const rcc_periph_clken_RCC_ADC1 : rcc_periph_clken = 777 ; pub const rcc_periph_clken_RCC_ADC2 : rcc_periph_clken = 778 ; pub const rcc_periph_clken_RCC_TIM1 : rcc_periph_clken = 779 ; pub const rcc_periph_clken_RCC_SPI1 : rcc_periph_clken = 780 ; pub const rcc_periph_clken_RCC_TIM8 : rcc_periph_clken = 781 ; pub const rcc_periph_clken_RCC_USART1 : rcc_periph_clken = 782 ; pub const rcc_periph_clken_RCC_ADC3 : rcc_periph_clken = 783 ; pub const rcc_periph_clken_RCC_TIM15 : rcc_periph_clken = 784 ; pub const rcc_periph_clken_RCC_TIM16 : rcc_periph_clken = 785 ; pub const rcc_periph_clken_RCC_TIM17 : rcc_periph_clken = 786 ; pub const rcc_periph_clken_RCC_TIM9 : rcc_periph_clken = 787 ; pub const rcc_periph_clken_RCC_TIM10 : rcc_periph_clken = 788 ; pub const rcc_periph_clken_RCC_TIM11 : rcc_periph_clken = 789 ; pub const rcc_periph_clken_RCC_TIM2 : rcc_periph_clken = 896 ; pub const rcc_periph_clken_RCC_TIM3 : rcc_periph_clken = 897 ; pub const rcc_periph_clken_RCC_TIM4 : rcc_periph_clken = 898 ; pub const rcc_periph_clken_RCC_TIM5 : rcc_periph_clken = 899 ; pub const rcc_periph_clken_RCC_TIM6 : rcc_periph_clken = 900 ; pub const rcc_periph_clken_RCC_TIM7 : rcc_periph_clken = 901 ; pub const rcc_periph_clken_RCC_TIM12 : rcc_periph_clken = 902 ; pub const rcc_periph_clken_RCC_TIM13 : rcc_periph_clken = 903 ; pub const rcc_periph_clken_RCC_TIM14 : rcc_periph_clken = 904 ; pub const rcc_periph_clken_RCC_WWDG : rcc_periph_clken = 907 ; pub const rcc_periph_clken_RCC_SPI2 : rcc_periph_clken = 910 ; pub const rcc_periph_clken_RCC_SPI3 : rcc_periph_clken = 911 ; pub const rcc_periph_clken_RCC_USART2 : rcc_periph_clken = 913 ; pub const rcc_periph_clken_RCC_USART3 : rcc_periph_clken = 914 ; pub const rcc_periph_clken_RCC_UART4 : rcc_periph_clken = 915 ; pub const rcc_periph_clken_RCC_UART5 : rcc_periph_clken = 916 ; pub const rcc_periph_clken_RCC_I2C1 : rcc_periph_clken = 917 ; pub const rcc_periph_clken_RCC_I2C2 : rcc_periph_clken = 918 ; pub const rcc_periph_clken_RCC_USB : rcc_periph_clken = 919 ; pub const rcc_periph_clken_RCC_CAN : rcc_periph_clken = 921 ; pub const rcc_periph_clken_RCC_CAN1 : rcc_periph_clken = 921 ; pub const rcc_periph_clken_RCC_CAN2 : rcc_periph_clken = 922 ; pub const rcc_periph_clken_RCC_BKP : rcc_periph_clken = 923 ; pub const rcc_periph_clken_RCC_PWR : rcc_periph_clken = 924 ; pub const rcc_periph_clken_RCC_DAC : rcc_periph_clken = 925 ; pub const rcc_periph_clken_RCC_CEC : rcc_periph_clken = 926 ; pub type rcc_periph_clken = u32 ; pub const rcc_periph_rst_RST_OTGFS : rcc_periph_rst = 1292 ; pub const rcc_periph_rst_RST_ETHMAC : rcc_periph_rst = 1294 ; pub const rcc_periph_rst_RST_AFIO : rcc_periph_rst = 384 ; pub const rcc_periph_rst_RST_GPIOA : rcc_periph_rst = 386 ; pub const rcc_periph_rst_RST_GPIOB : rcc_periph_rst = 387 ; pub const rcc_periph_rst_RST_GPIOC : rcc_periph_rst = 388 ; pub const rcc_periph_rst_RST_GPIOD : rcc_periph_rst = 389 ; pub const rcc_periph_rst_RST_GPIOE : rcc_periph_rst = 390 ; pub const rcc_periph_rst_RST_GPIOF : rcc_periph_rst = 391 ; pub const rcc_periph_rst_RST_GPIOG : rcc_periph_rst = 392 ; pub const rcc_periph_rst_RST_ADC1 : rcc_periph_rst = 393 ; pub const rcc_periph_rst_RST_ADC2 : rcc_periph_rst = 394 ; pub const rcc_periph_rst_RST_TIM1 : rcc_periph_rst = 395 ; pub const rcc_periph_rst_RST_SPI1 : rcc_periph_rst = 396 ; pub const rcc_periph_rst_RST_TIM8 : rcc_periph_rst = 397 ; pub const rcc_periph_rst_RST_USART1 : rcc_periph_rst = 398 ; pub const rcc_periph_rst_RST_ADC3 : rcc_periph_rst = 399 ; pub const rcc_periph_rst_RST_TIM15 : rcc_periph_rst = 400 ; pub const rcc_periph_rst_RST_TIM16 : rcc_periph_rst = 401 ; pub const rcc_periph_rst_RST_TIM17 : rcc_periph_rst = 402 ; pub const rcc_periph_rst_RST_TIM9 : rcc_periph_rst = 403 ; pub const rcc_periph_rst_RST_TIM10 : rcc_periph_rst = 404 ; pub const rcc_periph_rst_RST_TIM11 : rcc_periph_rst = 405 ; pub const rcc_periph_rst_RST_TIM2 : rcc_periph_rst = 512 ; pub const rcc_periph_rst_RST_TIM3 : rcc_periph_rst = 513 ; pub const rcc_periph_rst_RST_TIM4 : rcc_periph_rst = 514 ; pub const rcc_periph_rst_RST_TIM5 : rcc_periph_rst = 515 ; pub const rcc_periph_rst_RST_TIM6 : rcc_periph_rst = 516 ; pub const rcc_periph_rst_RST_TIM7 : rcc_periph_rst = 517 ; pub const rcc_periph_rst_RST_TIM12 : rcc_periph_rst = 518 ; pub const rcc_periph_rst_RST_TIM13 : rcc_periph_rst = 519 ; pub const rcc_periph_rst_RST_TIM14 : rcc_periph_rst = 520 ; pub const rcc_periph_rst_RST_WWDG : rcc_periph_rst = 523 ; pub const rcc_periph_rst_RST_SPI2 : rcc_periph_rst = 526 ; pub const rcc_periph_rst_RST_SPI3 : rcc_periph_rst = 527 ; pub const rcc_periph_rst_RST_USART2 : rcc_periph_rst = 529 ; pub const rcc_periph_rst_RST_USART3 : rcc_periph_rst = 530 ; pub const rcc_periph_rst_RST_UART4 : rcc_periph_rst = 531 ; pub const rcc_periph_rst_RST_UART5 : rcc_periph_rst = 532 ; pub const rcc_periph_rst_RST_I2C1 : rcc_periph_rst = 533 ; pub const rcc_periph_rst_RST_I2C2 : rcc_periph_rst = 534 ; pub const rcc_periph_rst_RST_USB : rcc_periph_rst = 535 ; pub const rcc_periph_rst_RST_CAN : rcc_periph_rst = 537 ; pub const rcc_periph_rst_RST_CAN1 : rcc_periph_rst = 537 ; pub const rcc_periph_rst_RST_CAN2 : rcc_periph_rst = 538 ; pub const rcc_periph_rst_RST_BKP : rcc_periph_rst = 539 ; pub const rcc_periph_rst_RST_PWR : rcc_periph_rst = 540 ; pub const rcc_periph_rst_RST_DAC : rcc_periph_rst = 541 ; pub const rcc_periph_rst_RST_CEC : rcc_periph_rst = 542 ; pub type rcc_periph_rst = u32 ; extern "C" { 
 /// @{ 
 pub fn rcc_peripheral_enable_clock ( reg : * mut u32 , en : u32 ) ; } extern "C" { pub fn rcc_peripheral_disable_clock ( reg : * mut u32 , en : u32 ) ; } extern "C" { pub fn rcc_peripheral_reset ( reg : * mut u32 , reset : u32 ) ; } extern "C" { pub fn rcc_peripheral_clear_reset ( reg : * mut u32 , clear_reset : u32 ) ; } extern "C" { pub fn rcc_periph_clock_enable ( clken : rcc_periph_clken ) ; } extern "C" { pub fn rcc_periph_clock_disable ( clken : rcc_periph_clken ) ; } extern "C" { pub fn rcc_periph_reset_pulse ( rst : rcc_periph_rst ) ; } extern "C" { pub fn rcc_periph_reset_hold ( rst : rcc_periph_rst ) ; } extern "C" { pub fn rcc_periph_reset_release ( rst : rcc_periph_rst ) ; } extern "C" { pub fn rcc_set_mco ( mcosrc : u32 ) ; } extern "C" { pub fn rcc_osc_bypass_enable ( osc : rcc_osc ) ; } extern "C" { pub fn rcc_osc_bypass_disable ( osc : rcc_osc ) ; } extern "C" { 
 /// Is the given oscillator ready?
/// @param osc Oscillator ID
/// @return true if the hardware indicates the oscillator is ready. 
 pub fn rcc_is_osc_ready ( osc : rcc_osc ) -> bool ; } extern "C" { 
 /// Wait for Oscillator Ready.
/// Block until the hardware indicates that the Oscillator is ready.
/// @param osc Oscillator ID 
 pub fn rcc_wait_for_osc_ready ( osc : rcc_osc ) ; } extern "C" { pub fn rcc_osc_ready_int_clear ( osc : rcc_osc ) ; } extern "C" { pub fn rcc_osc_ready_int_enable ( osc : rcc_osc ) ; } extern "C" { pub fn rcc_osc_ready_int_disable ( osc : rcc_osc ) ; } extern "C" { pub fn rcc_osc_ready_int_flag ( osc : rcc_osc ) -> raw_c_types :: c_int ; } extern "C" { pub fn rcc_css_int_clear ( ) ; } extern "C" { pub fn rcc_css_int_flag ( ) -> raw_c_types :: c_int ; } extern "C" { pub fn rcc_osc_on ( osc : rcc_osc ) ; } extern "C" { pub fn rcc_osc_off ( osc : rcc_osc ) ; } extern "C" { pub fn rcc_css_enable ( ) ; } extern "C" { pub fn rcc_css_disable ( ) ; } extern "C" { pub fn rcc_set_sysclk_source ( clk : u32 ) ; } extern "C" { pub fn rcc_set_pll_multiplication_factor ( mul : u32 ) ; } extern "C" { pub fn rcc_set_pll2_multiplication_factor ( mul : u32 ) ; } extern "C" { pub fn rcc_set_pll3_multiplication_factor ( mul : u32 ) ; } extern "C" { pub fn rcc_set_pll_source ( pllsrc : u32 ) ; } extern "C" { pub fn rcc_set_pllxtpre ( pllxtpre : u32 ) ; } extern "C" { pub fn rcc_rtc_clock_enabled_flag ( ) -> u32 ; } extern "C" { pub fn rcc_enable_rtc_clock ( ) ; } extern "C" { pub fn rcc_set_rtc_clock_source ( clock_source : rcc_osc ) ; } extern "C" { pub fn rcc_set_adcpre ( adcpre : u32 ) ; } extern "C" { pub fn rcc_set_ppre2 ( ppre2 : u32 ) ; } extern "C" { pub fn rcc_set_ppre1 ( ppre1 : u32 ) ; } extern "C" { pub fn rcc_set_hpre ( hpre : u32 ) ; } extern "C" { pub fn rcc_set_usbpre ( usbpre : u32 ) ; } extern "C" { pub fn rcc_set_prediv1 ( prediv : u32 ) ; } extern "C" { pub fn rcc_set_prediv2 ( prediv : u32 ) ; } extern "C" { pub fn rcc_set_prediv1_source ( rccsrc : u32 ) ; } extern "C" { pub fn rcc_system_clock_source ( ) -> u32 ; } extern "C" { pub fn rcc_clock_setup_in_hsi_out_64mhz ( ) ; } extern "C" { pub fn rcc_clock_setup_in_hsi_out_48mhz ( ) ; } extern "C" { pub fn rcc_clock_setup_in_hsi_out_24mhz ( ) ; } extern "C" { pub fn rcc_clock_setup_in_hse_8mhz_out_24mhz ( ) ; } extern "C" { pub fn rcc_clock_setup_in_hse_8mhz_out_72mhz ( ) ; } extern "C" { pub fn rcc_clock_setup_in_hse_12mhz_out_72mhz ( ) ; } extern "C" { pub fn rcc_clock_setup_in_hse_16mhz_out_72mhz ( ) ; } extern "C" { pub fn rcc_clock_setup_in_hse_25mhz_out_72mhz ( ) ; } extern "C" { pub fn rcc_backupdomain_reset ( ) ; } 
 /// Counter Second Flag 
 pub const rtcflag_t_RTC_SEC : rtcflag_t = 0 ; 
 /// Alarm Event Flag 
 pub const rtcflag_t_RTC_ALR : rtcflag_t = 1 ; 
 /// Counter Overflow Flag 
 pub const rtcflag_t_RTC_OW : rtcflag_t = 2 ; 
 /// RTC Interrupt Flags 
 pub type rtcflag_t = u32 ; extern "C" { pub fn rtc_awake_from_off ( clock_source : rcc_osc ) ; } extern "C" { pub fn rtc_enter_config_mode ( ) ; } extern "C" { pub fn rtc_exit_config_mode ( ) ; } extern "C" { pub fn rtc_set_alarm_time ( alarm_time : u32 ) ; } extern "C" { pub fn rtc_enable_alarm ( ) ; } extern "C" { pub fn rtc_disable_alarm ( ) ; } extern "C" { pub fn rtc_set_prescale_val ( prescale_val : u32 ) ; } extern "C" { pub fn rtc_get_counter_val ( ) -> u32 ; } extern "C" { pub fn rtc_get_prescale_div_val ( ) -> u32 ; } extern "C" { pub fn rtc_get_alarm_val ( ) -> u32 ; } extern "C" { pub fn rtc_set_counter_val ( counter_val : u32 ) ; } extern "C" { pub fn rtc_interrupt_enable ( flag_val : rtcflag_t ) ; } extern "C" { pub fn rtc_interrupt_disable ( flag_val : rtcflag_t ) ; } extern "C" { pub fn rtc_clear_flag ( flag_val : rtcflag_t ) ; } extern "C" { pub fn rtc_check_flag ( flag_val : rtcflag_t ) -> u32 ; } extern "C" { pub fn rtc_awake_from_standby ( ) ; } extern "C" { pub fn rtc_auto_awake ( clock_source : rcc_osc , prescale_val : u32 ) ; } extern "C" { pub fn spi_reset ( spi_peripheral : u32 ) ; } extern "C" { pub fn spi_enable ( spi : u32 ) ; } extern "C" { pub fn spi_disable ( spi : u32 ) ; } extern "C" { pub fn spi_clean_disable ( spi : u32 ) -> u16 ; } extern "C" { pub fn spi_write ( spi : u32 , data : u16 ) ; } extern "C" { pub fn spi_send ( spi : u32 , data : u16 ) ; } extern "C" { pub fn spi_read ( spi : u32 ) -> u16 ; } extern "C" { pub fn spi_xfer ( spi : u32 , data : u16 ) -> u16 ; } extern "C" { pub fn spi_set_bidirectional_mode ( spi : u32 ) ; } extern "C" { pub fn spi_set_unidirectional_mode ( spi : u32 ) ; } extern "C" { pub fn spi_set_bidirectional_receive_only_mode ( spi : u32 ) ; } extern "C" { pub fn spi_set_bidirectional_transmit_only_mode ( spi : u32 ) ; } extern "C" { pub fn spi_enable_crc ( spi : u32 ) ; } extern "C" { pub fn spi_disable_crc ( spi : u32 ) ; } extern "C" { pub fn spi_set_next_tx_from_buffer ( spi : u32 ) ; } extern "C" { pub fn spi_set_next_tx_from_crc ( spi : u32 ) ; } extern "C" { pub fn spi_set_full_duplex_mode ( spi : u32 ) ; } extern "C" { pub fn spi_set_receive_only_mode ( spi : u32 ) ; } extern "C" { pub fn spi_disable_software_slave_management ( spi : u32 ) ; } extern "C" { pub fn spi_enable_software_slave_management ( spi : u32 ) ; } extern "C" { pub fn spi_set_nss_high ( spi : u32 ) ; } extern "C" { pub fn spi_set_nss_low ( spi : u32 ) ; } extern "C" { pub fn spi_send_lsb_first ( spi : u32 ) ; } extern "C" { pub fn spi_send_msb_first ( spi : u32 ) ; } extern "C" { pub fn spi_set_baudrate_prescaler ( spi : u32 , baudrate : u8 ) ; } extern "C" { pub fn spi_set_master_mode ( spi : u32 ) ; } extern "C" { pub fn spi_set_slave_mode ( spi : u32 ) ; } extern "C" { pub fn spi_set_clock_polarity_1 ( spi : u32 ) ; } extern "C" { pub fn spi_set_clock_polarity_0 ( spi : u32 ) ; } extern "C" { pub fn spi_set_clock_phase_1 ( spi : u32 ) ; } extern "C" { pub fn spi_set_clock_phase_0 ( spi : u32 ) ; } extern "C" { pub fn spi_enable_tx_buffer_empty_interrupt ( spi : u32 ) ; } extern "C" { pub fn spi_disable_tx_buffer_empty_interrupt ( spi : u32 ) ; } extern "C" { pub fn spi_enable_rx_buffer_not_empty_interrupt ( spi : u32 ) ; } extern "C" { pub fn spi_disable_rx_buffer_not_empty_interrupt ( spi : u32 ) ; } extern "C" { pub fn spi_enable_error_interrupt ( spi : u32 ) ; } extern "C" { pub fn spi_disable_error_interrupt ( spi : u32 ) ; } extern "C" { pub fn spi_enable_ss_output ( spi : u32 ) ; } extern "C" { pub fn spi_disable_ss_output ( spi : u32 ) ; } extern "C" { pub fn spi_enable_tx_dma ( spi : u32 ) ; } extern "C" { pub fn spi_disable_tx_dma ( spi : u32 ) ; } extern "C" { pub fn spi_enable_rx_dma ( spi : u32 ) ; } extern "C" { pub fn spi_disable_rx_dma ( spi : u32 ) ; } extern "C" { pub fn spi_set_standard_mode ( spi : u32 , mode : u8 ) ; } extern "C" { pub fn spi_init_master ( spi : u32 , br : u32 , cpol : u32 , cpha : u32 , dff : u32 , lsbfirst : u32 ) -> raw_c_types :: c_int ; } extern "C" { pub fn spi_set_dff_8bit ( spi : u32 ) ; } extern "C" { pub fn spi_set_dff_16bit ( spi : u32 ) ; } pub const tim_oc_id_TIM_OC1 : tim_oc_id = 0 ; pub const tim_oc_id_TIM_OC1N : tim_oc_id = 1 ; pub const tim_oc_id_TIM_OC2 : tim_oc_id = 2 ; pub const tim_oc_id_TIM_OC2N : tim_oc_id = 3 ; pub const tim_oc_id_TIM_OC3 : tim_oc_id = 4 ; pub const tim_oc_id_TIM_OC3N : tim_oc_id = 5 ; pub const tim_oc_id_TIM_OC4 : tim_oc_id = 6 ; 
 /// Output Compare channel designators 
 pub type tim_oc_id = u32 ; pub const tim_oc_mode_TIM_OCM_FROZEN : tim_oc_mode = 0 ; pub const tim_oc_mode_TIM_OCM_ACTIVE : tim_oc_mode = 1 ; pub const tim_oc_mode_TIM_OCM_INACTIVE : tim_oc_mode = 2 ; pub const tim_oc_mode_TIM_OCM_TOGGLE : tim_oc_mode = 3 ; pub const tim_oc_mode_TIM_OCM_FORCE_LOW : tim_oc_mode = 4 ; pub const tim_oc_mode_TIM_OCM_FORCE_HIGH : tim_oc_mode = 5 ; pub const tim_oc_mode_TIM_OCM_PWM1 : tim_oc_mode = 6 ; pub const tim_oc_mode_TIM_OCM_PWM2 : tim_oc_mode = 7 ; 
 /// Output Compare mode designators 
 pub type tim_oc_mode = u32 ; pub const tim_ic_id_TIM_IC1 : tim_ic_id = 0 ; pub const tim_ic_id_TIM_IC2 : tim_ic_id = 1 ; pub const tim_ic_id_TIM_IC3 : tim_ic_id = 2 ; pub const tim_ic_id_TIM_IC4 : tim_ic_id = 3 ; 
 /// Input Capture channel designators 
 pub type tim_ic_id = u32 ; pub const tim_ic_filter_TIM_IC_OFF : tim_ic_filter = 0 ; pub const tim_ic_filter_TIM_IC_CK_INT_N_2 : tim_ic_filter = 1 ; pub const tim_ic_filter_TIM_IC_CK_INT_N_4 : tim_ic_filter = 2 ; pub const tim_ic_filter_TIM_IC_CK_INT_N_8 : tim_ic_filter = 3 ; pub const tim_ic_filter_TIM_IC_DTF_DIV_2_N_6 : tim_ic_filter = 4 ; pub const tim_ic_filter_TIM_IC_DTF_DIV_2_N_8 : tim_ic_filter = 5 ; pub const tim_ic_filter_TIM_IC_DTF_DIV_4_N_6 : tim_ic_filter = 6 ; pub const tim_ic_filter_TIM_IC_DTF_DIV_4_N_8 : tim_ic_filter = 7 ; pub const tim_ic_filter_TIM_IC_DTF_DIV_8_N_6 : tim_ic_filter = 8 ; pub const tim_ic_filter_TIM_IC_DTF_DIV_8_N_8 : tim_ic_filter = 9 ; pub const tim_ic_filter_TIM_IC_DTF_DIV_16_N_5 : tim_ic_filter = 10 ; pub const tim_ic_filter_TIM_IC_DTF_DIV_16_N_6 : tim_ic_filter = 11 ; pub const tim_ic_filter_TIM_IC_DTF_DIV_16_N_8 : tim_ic_filter = 12 ; pub const tim_ic_filter_TIM_IC_DTF_DIV_32_N_5 : tim_ic_filter = 13 ; pub const tim_ic_filter_TIM_IC_DTF_DIV_32_N_6 : tim_ic_filter = 14 ; pub const tim_ic_filter_TIM_IC_DTF_DIV_32_N_8 : tim_ic_filter = 15 ; 
 /// Input Capture input filter. The frequency used to sample the
/// input and the number of events needed to validate an output transition.
///
/// TIM_IC_CK_INT_N_x No division from the Deadtime and Sampling Clock frequency
/// (DTF), filter length x
/// TIM_IC_DTF_DIV_y_N_x Division by y from the DTF, filter length x 
 pub type tim_ic_filter = u32 ; pub const tim_ic_psc_TIM_IC_PSC_OFF : tim_ic_psc = 0 ; pub const tim_ic_psc_TIM_IC_PSC_2 : tim_ic_psc = 1 ; pub const tim_ic_psc_TIM_IC_PSC_4 : tim_ic_psc = 2 ; pub const tim_ic_psc_TIM_IC_PSC_8 : tim_ic_psc = 3 ; 
 /// Input Capture input prescaler.
///
/// TIM_IC_PSC_x Input capture is done every x events 
 pub type tim_ic_psc = u32 ; pub const tim_ic_input_TIM_IC_OUT : tim_ic_input = 0 ; pub const tim_ic_input_TIM_IC_IN_TI1 : tim_ic_input = 1 ; pub const tim_ic_input_TIM_IC_IN_TI2 : tim_ic_input = 2 ; pub const tim_ic_input_TIM_IC_IN_TRC : tim_ic_input = 3 ; pub const tim_ic_input_TIM_IC_IN_TI3 : tim_ic_input = 5 ; pub const tim_ic_input_TIM_IC_IN_TI4 : tim_ic_input = 6 ; 
 /// Input Capture input source.
///
/// The direction of the channel (input/output) as well as the input used. 
 pub type tim_ic_input = u32 ; pub const tim_et_pol_TIM_ET_RISING : tim_et_pol = 0 ; pub const tim_et_pol_TIM_ET_FALLING : tim_et_pol = 1 ; 
 /// Slave external trigger polarity 
 pub type tim_et_pol = u32 ; extern "C" { pub fn timer_enable_irq ( timer_peripheral : u32 , irq : u32 ) ; } extern "C" { pub fn timer_disable_irq ( timer_peripheral : u32 , irq : u32 ) ; } extern "C" { pub fn timer_interrupt_source ( timer_peripheral : u32 , flag : u32 ) -> bool ; } extern "C" { pub fn timer_get_flag ( timer_peripheral : u32 , flag : u32 ) -> bool ; } extern "C" { pub fn timer_clear_flag ( timer_peripheral : u32 , flag : u32 ) ; } extern "C" { pub fn timer_set_mode ( timer_peripheral : u32 , clock_div : u32 , alignment : u32 , direction : u32 ) ; } extern "C" { pub fn timer_set_clock_division ( timer_peripheral : u32 , clock_div : u32 ) ; } extern "C" { pub fn timer_enable_preload ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_disable_preload ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_set_alignment ( timer_peripheral : u32 , alignment : u32 ) ; } extern "C" { pub fn timer_direction_up ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_direction_down ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_one_shot_mode ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_continuous_mode ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_update_on_any ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_update_on_overflow ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_enable_update_event ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_disable_update_event ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_enable_counter ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_disable_counter ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_set_output_idle_state ( timer_peripheral : u32 , outputs : u32 ) ; } extern "C" { pub fn timer_reset_output_idle_state ( timer_peripheral : u32 , outputs : u32 ) ; } extern "C" { pub fn timer_set_ti1_ch123_xor ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_set_ti1_ch1 ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_set_master_mode ( timer_peripheral : u32 , mode : u32 ) ; } extern "C" { pub fn timer_set_dma_on_compare_event ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_set_dma_on_update_event ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_enable_compare_control_update_on_trigger ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_disable_compare_control_update_on_trigger ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_enable_preload_complementry_enable_bits ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_disable_preload_complementry_enable_bits ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_set_prescaler ( timer_peripheral : u32 , value : u32 ) ; } extern "C" { pub fn timer_set_repetition_counter ( timer_peripheral : u32 , value : u32 ) ; } extern "C" { pub fn timer_set_period ( timer_peripheral : u32 , period : u32 ) ; } extern "C" { pub fn timer_enable_oc_clear ( timer_peripheral : u32 , oc_id : tim_oc_id ) ; } extern "C" { pub fn timer_disable_oc_clear ( timer_peripheral : u32 , oc_id : tim_oc_id ) ; } extern "C" { pub fn timer_set_oc_fast_mode ( timer_peripheral : u32 , oc_id : tim_oc_id ) ; } extern "C" { pub fn timer_set_oc_slow_mode ( timer_peripheral : u32 , oc_id : tim_oc_id ) ; } extern "C" { pub fn timer_set_oc_mode ( timer_peripheral : u32 , oc_id : tim_oc_id , oc_mode : tim_oc_mode ) ; } extern "C" { pub fn timer_enable_oc_preload ( timer_peripheral : u32 , oc_id : tim_oc_id ) ; } extern "C" { pub fn timer_disable_oc_preload ( timer_peripheral : u32 , oc_id : tim_oc_id ) ; } extern "C" { pub fn timer_set_oc_polarity_high ( timer_peripheral : u32 , oc_id : tim_oc_id ) ; } extern "C" { pub fn timer_set_oc_polarity_low ( timer_peripheral : u32 , oc_id : tim_oc_id ) ; } extern "C" { pub fn timer_enable_oc_output ( timer_peripheral : u32 , oc_id : tim_oc_id ) ; } extern "C" { pub fn timer_disable_oc_output ( timer_peripheral : u32 , oc_id : tim_oc_id ) ; } extern "C" { pub fn timer_set_oc_idle_state_set ( timer_peripheral : u32 , oc_id : tim_oc_id ) ; } extern "C" { pub fn timer_set_oc_idle_state_unset ( timer_peripheral : u32 , oc_id : tim_oc_id ) ; } extern "C" { pub fn timer_set_oc_value ( timer_peripheral : u32 , oc_id : tim_oc_id , value : u32 ) ; } extern "C" { pub fn timer_enable_break_main_output ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_disable_break_main_output ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_enable_break_automatic_output ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_disable_break_automatic_output ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_set_break_polarity_high ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_set_break_polarity_low ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_enable_break ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_disable_break ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_set_enabled_off_state_in_run_mode ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_set_disabled_off_state_in_run_mode ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_set_enabled_off_state_in_idle_mode ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_set_disabled_off_state_in_idle_mode ( timer_peripheral : u32 ) ; } extern "C" { pub fn timer_set_break_lock ( timer_peripheral : u32 , lock : u32 ) ; } extern "C" { pub fn timer_set_deadtime ( timer_peripheral : u32 , deadtime : u32 ) ; } extern "C" { pub fn timer_generate_event ( timer_peripheral : u32 , event : u32 ) ; } extern "C" { pub fn timer_get_counter ( timer_peripheral : u32 ) -> u32 ; } extern "C" { pub fn timer_set_counter ( timer_peripheral : u32 , count : u32 ) ; } extern "C" { pub fn timer_ic_set_filter ( timer : u32 , ic : tim_ic_id , flt : tim_ic_filter ) ; } extern "C" { pub fn timer_ic_set_prescaler ( timer : u32 , ic : tim_ic_id , psc : tim_ic_psc ) ; } extern "C" { pub fn timer_ic_set_input ( timer : u32 , ic : tim_ic_id , in_ : tim_ic_input ) ; } extern "C" { pub fn timer_ic_enable ( timer : u32 , ic : tim_ic_id ) ; } extern "C" { pub fn timer_ic_disable ( timer : u32 , ic : tim_ic_id ) ; } extern "C" { pub fn timer_slave_set_filter ( timer : u32 , flt : tim_ic_filter ) ; } extern "C" { pub fn timer_slave_set_prescaler ( timer : u32 , psc : tim_ic_psc ) ; } extern "C" { pub fn timer_slave_set_polarity ( timer : u32 , pol : tim_et_pol ) ; } extern "C" { pub fn timer_slave_set_mode ( timer : u32 , mode : u8 ) ; } extern "C" { pub fn timer_slave_set_trigger ( timer : u32 , trigger : u8 ) ; } pub const tim_ic_pol_TIM_IC_RISING : tim_ic_pol = 0 ; pub const tim_ic_pol_TIM_IC_FALLING : tim_ic_pol = 1 ; 
 /// Input Capture input polarity 
 pub type tim_ic_pol = u32 ; extern "C" { pub fn timer_ic_set_polarity ( timer : u32 , ic : tim_ic_id , pol : tim_ic_pol ) ; } extern "C" { pub fn usart_set_baudrate ( usart : u32 , baud : u32 ) ; } extern "C" { pub fn usart_set_databits ( usart : u32 , bits : u32 ) ; } extern "C" { pub fn usart_set_stopbits ( usart : u32 , stopbits : u32 ) ; } extern "C" { pub fn usart_set_parity ( usart : u32 , parity : u32 ) ; } extern "C" { pub fn usart_set_mode ( usart : u32 , mode : u32 ) ; } extern "C" { pub fn usart_set_flow_control ( usart : u32 , flowcontrol : u32 ) ; } extern "C" { pub fn usart_enable ( usart : u32 ) ; } extern "C" { pub fn usart_disable ( usart : u32 ) ; } extern "C" { pub fn usart_send ( usart : u32 , data : u16 ) ; } extern "C" { pub fn usart_recv ( usart : u32 ) -> u16 ; } extern "C" { pub fn usart_wait_send_ready ( usart : u32 ) ; } extern "C" { pub fn usart_wait_recv_ready ( usart : u32 ) ; } extern "C" { pub fn usart_send_blocking ( usart : u32 , data : u16 ) ; } extern "C" { pub fn usart_recv_blocking ( usart : u32 ) -> u16 ; } extern "C" { pub fn usart_enable_rx_dma ( usart : u32 ) ; } extern "C" { pub fn usart_disable_rx_dma ( usart : u32 ) ; } extern "C" { pub fn usart_enable_tx_dma ( usart : u32 ) ; } extern "C" { pub fn usart_disable_tx_dma ( usart : u32 ) ; } extern "C" { pub fn usart_enable_rx_interrupt ( usart : u32 ) ; } extern "C" { pub fn usart_disable_rx_interrupt ( usart : u32 ) ; } extern "C" { pub fn usart_enable_tx_interrupt ( usart : u32 ) ; } extern "C" { pub fn usart_disable_tx_interrupt ( usart : u32 ) ; } extern "C" { pub fn usart_enable_error_interrupt ( usart : u32 ) ; } extern "C" { pub fn usart_disable_error_interrupt ( usart : u32 ) ; } extern "C" { pub fn usart_get_flag ( usart : u32 , flag : u32 ) -> bool ; }