Crate imxrt1062_semc

Modules

bmcr0	Master Bus (AXI) Control Register 0
bmcr1	Master Bus (AXI) Control Register 1
br0	Base Register 0 (For SDRAM CS0 device)
br1	Base Register 1 (For SDRAM CS1 device)
br2	Base Register 2 (For SDRAM CS2 device)
br3	Base Register 3 (For SDRAM CS3 device)
br4	Base Register 4 (For NAND device)
br5	Base Register 5 (For NOR device)
br6	Base Register 6 (For PSRAM device)
br7	Base Register 7 (For DBI-B (MIPI Display Bus Interface Type B) device)
br8	Base Register 8 (For NAND device)
dbicr0	DBI-B control register 0
dbicr1	DBI-B control register 1
dllcr	DLL Control Register
inten	Interrupt Enable Register
intr	Interrupt Enable Register
iocr	IO Mux Control Register
ipcmd	IP Command register
ipcr0	IP Command control register 0
ipcr1	IP Command control register 1
ipcr2	IP Command control register 2
iprxdat	RX DATA register (for IP Command)
iptxdat	TX DATA register (for IP Command)
mcr	Module Control Register
nandcr0	NAND control register 0
nandcr1	NAND control register 1
nandcr2	NAND control register 2
nandcr3	NAND control register 3
norcr0	NOR control register 0
norcr1	NOR control register 1
norcr2	NOR control register 2
norcr3	NOR control register 3
sdramcr0	SDRAM control register 0
sdramcr1	SDRAM control register 1
sdramcr2	SDRAM control register 2
sdramcr3	SDRAM control register 3
sramcr0	SRAM control register 0
sramcr1	SRAM control register 1
sramcr2	SRAM control register 2
sramcr3	SRAM control register 3
sts0	Status register 0
sts1	Status register 1
sts2	Status register 2
sts3	Status register 3
sts4	Status register 4
sts5	Status register 5
sts6	Status register 6
sts7	Status register 7
sts8	Status register 8
sts9	Status register 9
sts10	Status register 10
sts11	Status register 11
sts12	Status register 12
sts13	Status register 13
sts14	Status register 14
sts15	Status register 15

Structs

R	Register/field reader
Reg	This structure provides volatile access to register
RegisterBlock	Register block
W	Register writer

Enums

Variant

Used if enumerated values cover not the whole range

Traits

Readable	This trait shows that register has read method
ResetValue	Reset value of the register
Writable	This trait shows that register has write, write_with_zero and reset method

Type Definitions

BMCR0	Master Bus (AXI) Control Register 0
BMCR1	Master Bus (AXI) Control Register 1
BR0	Base Register 0 (For SDRAM CS0 device)
BR1	Base Register 1 (For SDRAM CS1 device)
BR2	Base Register 2 (For SDRAM CS2 device)
BR3	Base Register 3 (For SDRAM CS3 device)
BR4	Base Register 4 (For NAND device)
BR5	Base Register 5 (For NOR device)
BR6	Base Register 6 (For PSRAM device)
BR7	Base Register 7 (For DBI-B (MIPI Display Bus Interface Type B) device)
BR8	Base Register 8 (For NAND device)
DBICR0	DBI-B control register 0
DBICR1	DBI-B control register 1
DLLCR	DLL Control Register
INTEN	Interrupt Enable Register
INTR	Interrupt Enable Register
IOCR	IO Mux Control Register
IPCMD	IP Command register
IPCR0	IP Command control register 0
IPCR1	IP Command control register 1
IPCR2	IP Command control register 2
IPRXDAT	RX DATA register (for IP Command)
IPTXDAT	TX DATA register (for IP Command)
MCR	Module Control Register
NANDCR0	NAND control register 0
NANDCR1	NAND control register 1
NANDCR2	NAND control register 2
NANDCR3	NAND control register 3
NORCR0	NOR control register 0
NORCR1	NOR control register 1
NORCR2	NOR control register 2
NORCR3	NOR control register 3
SDRAMCR0	SDRAM control register 0
SDRAMCR1	SDRAM control register 1
SDRAMCR2	SDRAM control register 2
SDRAMCR3	SDRAM control register 3
SRAMCR0	SRAM control register 0
SRAMCR1	SRAM control register 1
SRAMCR2	SRAM control register 2
SRAMCR3	SRAM control register 3
STS0	Status register 0
STS1	Status register 1
STS2	Status register 2
STS3	Status register 3
STS4	Status register 4
STS5	Status register 5
STS6	Status register 6
STS7	Status register 7
STS8	Status register 8
STS9	Status register 9
STS10	Status register 10
STS11	Status register 11
STS12	Status register 12
STS13	Status register 13
STS14	Status register 14
STS15	Status register 15