Module imxrt1062_ccm::cs2cdr

CCM Clock Divider Register

Structs

SAI2_CLK_PODF_W	Write proxy for field SAI2_CLK_PODF
SAI2_CLK_PRED_W	Write proxy for field SAI2_CLK_PRED

Enums

SAI2_CLK_PODF_A	Divider for sai2 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this.
SAI2_CLK_PRED_A	Divider for sai2 clock pred.Divider should be updated when output clock is gated.

Type Definitions

R	Reader of register CS2CDR
SAI2_CLK_PODF_R	Reader of field SAI2_CLK_PODF
SAI2_CLK_PRED_R	Reader of field SAI2_CLK_PRED
W	Writer for register CS2CDR