[−][src]Module imxrt1062_ccm::cs1cdr
CCM Clock Divider Register
Structs
FLEXIO2_CLK_PRED_W | Write proxy for field |
FLEXIO2_CLK_PODF_W | Write proxy for field |
SAI1_CLK_PODF_W | Write proxy for field |
SAI1_CLK_PRED_W | Write proxy for field |
SAI3_CLK_PODF_W | Write proxy for field |
SAI3_CLK_PRED_W | Write proxy for field |
Enums
FLEXIO2_CLK_PRED_A | Divider for flexio2/flexio3 clock. |
FLEXIO2_CLK_PODF_A | Divider for flexio2/flexio3 clock. Divider should be updated when output clock is gated. |
SAI1_CLK_PODF_A | Divider for sai1 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. |
SAI1_CLK_PRED_A | Divider for sai1 clock pred. |
SAI3_CLK_PODF_A | Divider for sai3 clock podf. The input clock to this divider should be lower than 300Mhz, the predivider can be used to achieve this. |
SAI3_CLK_PRED_A | Divider for sai3/adc1/adc2 clock pred. |
Type Definitions
FLEXIO2_CLK_PRED_R | Reader of field |
FLEXIO2_CLK_PODF_R | Reader of field |
R | Reader of register CS1CDR |
SAI1_CLK_PODF_R | Reader of field |
SAI1_CLK_PRED_R | Reader of field |
SAI3_CLK_PODF_R | Reader of field |
SAI3_CLK_PRED_R | Reader of field |
W | Writer for register CS1CDR |