[][src]Module esp32::spi

SPI

Modules

cache_fctrl

SPI_CACHE_FCTRL

cache_sctrl

SPI_CACHE_SCTRL

clock

SPI_CLOCK

cmd

SPI_CMD

ctrl

SPI_CTRL

ctrl1

SPI_CTRL1

ctrl2

SPI_CTRL2

date

SPI_DATE

dma_conf

SPI_DMA_CONF

dma_in_link

SPI_DMA_IN_LINK

dma_int_clr

SPI_DMA_INT_CLR

dma_int_ena

SPI_DMA_INT_ENA

dma_int_raw

SPI_DMA_INT_RAW

dma_int_st

SPI_DMA_INT_ST

dma_out_link

SPI_DMA_OUT_LINK

dma_rstatus

SPI_DMA_RSTATUS

dma_status

SPI_DMA_STATUS

dma_tstatus

SPI_DMA_TSTATUS

ext0

SPI_EXT0

ext1

SPI_EXT1

ext2

SPI_EXT2

ext3

SPI_EXT3

in_err_eof_des_addr

SPI_IN_ERR_EOF_DES_ADDR

in_suc_eof_des_addr

SPI_IN_SUC_EOF_DES_ADDR

inlink_dscr

SPI_INLINK_DSCR

inlink_dscr_bf0

SPI_INLINK_DSCR_BF0

inlink_dscr_bf1

SPI_INLINK_DSCR_BF1

miso_dlen

SPI_MISO_DLEN

mosi_dlen

SPI_MOSI_DLEN

out_eof_bfr_des_addr

SPI_OUT_EOF_BFR_DES_ADDR

out_eof_des_addr

SPI_OUT_EOF_DES_ADDR

outlink_dscr

SPI_OUTLINK_DSCR

outlink_dscr_bf0

SPI_OUTLINK_DSCR_BF0

outlink_dscr_bf1

SPI_OUTLINK_DSCR_BF1

pin

SPI_PIN

rd_status

SPI_RD_STATUS

slave

SPI_SLAVE

slave1

SPI_SLAVE1

slave2

SPI_SLAVE2

slave3

SPI_SLAVE3

slv_rd_bit

SPI_SLV_RD_BIT

slv_rdbuf_dlen

SPI_SLV_RDBUF_DLEN

slv_wr_status

SPI_SLV_WR_STATUS

slv_wrbuf_dlen

SPI_SLV_WRBUF_DLEN

sram_cmd

SPI_SRAM_CMD

sram_drd_cmd

SPI_SRAM_DRD_CMD

sram_dwr_cmd

SPI_SRAM_DWR_CMD

tx_crc

SPI_TX_CRC

user

SPI_USER

user1

SPI_USER1

user2

SPI_USER2

w

SPI_W0

Structs

RegisterBlock

Register block

Type Definitions

CACHE_FCTRL

SPI_CACHE_FCTRL

CACHE_SCTRL

SPI_CACHE_SCTRL

CLOCK

SPI_CLOCK

CMD

SPI_CMD

CTRL

SPI_CTRL

CTRL1

SPI_CTRL1

CTRL2

SPI_CTRL2

DATE

SPI_DATE

DMA_CONF

SPI_DMA_CONF

DMA_INT_CLR

SPI_DMA_INT_CLR

DMA_INT_ENA

SPI_DMA_INT_ENA

DMA_INT_RAW

SPI_DMA_INT_RAW

DMA_INT_ST

SPI_DMA_INT_ST

DMA_IN_LINK

SPI_DMA_IN_LINK

DMA_OUT_LINK

SPI_DMA_OUT_LINK

DMA_RSTATUS

SPI_DMA_RSTATUS

DMA_STATUS

SPI_DMA_STATUS

DMA_TSTATUS

SPI_DMA_TSTATUS

EXT0

SPI_EXT0

EXT1

SPI_EXT1

EXT2

SPI_EXT2

EXT3

SPI_EXT3

INLINK_DSCR

SPI_INLINK_DSCR

INLINK_DSCR_BF0

SPI_INLINK_DSCR_BF0

INLINK_DSCR_BF1

SPI_INLINK_DSCR_BF1

IN_ERR_EOF_DES_ADDR

SPI_IN_ERR_EOF_DES_ADDR

IN_SUC_EOF_DES_ADDR

SPI_IN_SUC_EOF_DES_ADDR

MISO_DLEN

SPI_MISO_DLEN

MOSI_DLEN

SPI_MOSI_DLEN

OUTLINK_DSCR

SPI_OUTLINK_DSCR

OUTLINK_DSCR_BF0

SPI_OUTLINK_DSCR_BF0

OUTLINK_DSCR_BF1

SPI_OUTLINK_DSCR_BF1

OUT_EOF_BFR_DES_ADDR

SPI_OUT_EOF_BFR_DES_ADDR

OUT_EOF_DES_ADDR

SPI_OUT_EOF_DES_ADDR

PIN

SPI_PIN

RD_STATUS

SPI_RD_STATUS

SLAVE

SPI_SLAVE

SLAVE1

SPI_SLAVE1

SLAVE2

SPI_SLAVE2

SLAVE3

SPI_SLAVE3

SLV_RDBUF_DLEN

SPI_SLV_RDBUF_DLEN

SLV_RD_BIT

SPI_SLV_RD_BIT

SLV_WRBUF_DLEN

SPI_SLV_WRBUF_DLEN

SLV_WR_STATUS

SPI_SLV_WR_STATUS

SRAM_CMD

SPI_SRAM_CMD

SRAM_DRD_CMD

SPI_SRAM_DRD_CMD

SRAM_DWR_CMD

SPI_SRAM_DWR_CMD

TX_CRC

SPI_TX_CRC

USER

SPI_USER

USER1

SPI_USER1

USER2

SPI_USER2

W

SPI_W0