Crate e310x

source ·
Expand description

Peripheral access API for FE310 microcontrollers (generated using svd2rust v0.26.0 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports

  • pub use self::uart0 as uart1;
  • pub use self::qspi0 as qspi1;
  • pub use self::pwm0 as pwm1;
  • pub use self::qspi0 as qspi2;
  • pub use self::pwm0 as pwm2;

Modules

  • aonclk
    Always-On Clock Configuration
  • backup
    Backup Registers
  • clint
    Coreplex Local Interrupts
  • generic
    Common register and bit access and modify traits
  • gpio0
    General Purpose Input Output
  • i2c0
    Inter-Integrated Circuit Master Interface (FE310-G002 only)
  • otp
    One Time Programmable Memory
  • plic
    Platform Level Interrupt Control
  • pmu
    PMU
  • prci
    Power Reset Clock Interrupts
  • pwm0
    8-bit timer with 4 cmp
  • qspi0
    Quad Serial Peripheral Interface
  • rtc
    Watchdog
  • uart0
    Universal Asynchronous Receiver Transmitter
  • wdog
    Watchdog

Macros

Structs

  • AONCLK
    Always-On Clock Configuration
  • BACKUP
    Backup Registers
  • CLINT
    Coreplex Local Interrupts
  • GPIO0
    General Purpose Input Output
  • I2C0
    Inter-Integrated Circuit Master Interface (FE310-G002 only)
  • OTP
    One Time Programmable Memory
  • PLIC
    Platform Level Interrupt Control
  • PMU
    PMU
  • PRCI
    Power Reset Clock Interrupts
  • PWM0
    8-bit timer with 4 cmp
  • PWM1
    8-bit timer with 4 cmp
  • PWM2
    8-bit timer with 4 cmp
  • Peripherals
    All the peripherals.
  • QSPI0
    Quad Serial Peripheral Interface
  • QSPI1
    Quad Serial Peripheral Interface
  • QSPI2
    Quad Serial Peripheral Interface
  • RTC
    Watchdog
  • UART0
    Universal Asynchronous Receiver Transmitter
  • UART1
    Universal Asynchronous Receiver Transmitter
  • WDOG
    Watchdog

Enums