Struct cortex_m::peripheral::scb::Registers

pub struct Registers {
    pub icsr: RW<u32>,
    pub vtor: RW<u32>,
    pub aircr: RW<u32>,
    pub scr: RW<u32>,
    pub ccr: RW<u32>,
    pub shpr: [RW<u8>; 12],
    pub shpcrs: RW<u32>,
    pub cfsr: RW<u32>,
    pub hfsr: RW<u32>,
    pub dfsr: RW<u32>,
    pub mmar: RW<u32>,
    pub bfar: RW<u32>,
    pub afsr: RW<u32>,
    pub cpacr: RW<u32>,
    // some fields omitted
}

Registers

Fields

icsr: RW<u32>

Interrupt Control and State

vtor: RW<u32>

Vector Table Offset

aircr: RW<u32>

Application Interrupt and Reset Control

scr: RW<u32>

System Control

ccr: RW<u32>

Configuration and Control

shpr: [RW<u8>; 12]

System Handler Priority

shpcrs: RW<u32>

System Handler Control and State

cfsr: RW<u32>

Configurable Fault Status

hfsr: RW<u32>

HardFault Status

dfsr: RW<u32>

Debug Fault Status

mmar: RW<u32>

MemManage Fault Address

bfar: RW<u32>

BusFault Address

afsr: RW<u32>

Auxiliary Fault Status

cpacr: RW<u32>

Coprocessor Access Control