Module cortex_a::registers::SCTLR_EL1::A [−][src]
Expand description
Alignment check enable. This is the enable bit for Alignment fault checking at EL1 and EL0.
Instructions that load or store one or more registers, other than load/store exclusive and load-acquire/store-release, will or will not check that the address being accessed is aligned to the size of the data element(s) being accessed depending on this flag.
Load/store exclusive and load-acquire/store-release instructions have an alignment check regardless of the value of the A bit.
Enums
Alignment check enable. This is the enable bit for Alignment fault checking at EL1 and EL0.