Module cortex_a::registers::SCR_EL3::SMD

Secure Monitor call Disable

0 The SMC instruction is enabled at EL1, EL2, and EL3.

1 The SMC instruction is undefined at all exception levels. At EL1, in the Non-secure state, the HCR_EL2.TSC bit has priority over this control.

Enums

Value

Secure Monitor call Disable

Constants

CLEAR

SET

SmcDisabled

SmcEnabled