Module cortex_a::registers::SCR_EL3::RW [−][src]
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Execution state control for lower Exception levels:
0 Lower levels are all AArch32. 1 The next lower level is AArch64. If EL2 is present: The Execution state for EL2 is AArch64. EL2 controls EL1 and EL0 behaviors. If EL2 is not present: The Execution state for EL1 is AArch64. The Execution state for EL0 is determined by the current value of PSTATE.nRW when executing at EL0.
If all lower Exception levels cannot use AArch32 then this bit is RAO/WI.
When SCR_EL3.{EEL2,NS}=={1,0}, this bit is treated as 1 for all purposes other than reading or writing the register.
The RW bit is permitted to be cached in a TLB.
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Execution state control for lower Exception levels: