Module cortex_a::regs::TCR_EL2[−][src]

Modules

IRGN0	Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2.
ORGN0	Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2.
PS	Physical Address Size.
SH0	Shareability attribute for memory associated with translation table walks using TTBR0_EL2.
T0SZ	The size offset of the memory region addressed by TTBR0_EL2. The region size is 2^(64-T0SZ) bytes.
TBI	Top Byte ignored - indicates whether the top byte of an address is used for address match for the TTBR0_EL2 region, or ignored and used for tagged addresses. Defined values are:
TG0	Granule size for the TTBR0_EL2.