Module cortex_a::regs::TCR_EL1 [−][src]
Modules
| A1 | Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID. The encoding of this bit is: |
| AS | ASID Size. Defined values are: |
| EPD0 | Translation table walk disable for translations using TTBR0_EL1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR0_EL1. The encoding of this bit is: |
| EPD1 | Translation table walk disable for translations using TTBR1_EL1. This bit controls whether a translation table walk is performed on a TLB miss, for an address that is translated using TTBR1_EL1. The encoding of this bit is: |
| IPS | Intermediate Physical Address Size. |
| IRGN0 | Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. |
| IRGN1 | Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. |
| ORGN0 | Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. |
| ORGN1 | Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. |
| SH0 | Shareability attribute for memory associated with translation table walks using TTBR0_EL1. |
| SH1 | Shareability attribute for memory associated with translation table walks using TTBR1_EL1. |
| T0SZ | The size offset of the memory region addressed by TTBR0_EL1. The region size is 2^(64-T0SZ) bytes. |
| T1SZ | The size offset of the memory region addressed by TTBR1_EL1. The region size is 2^(64-T1SZ) bytes. |
| TBI0 | Top Byte ignored - indicates whether the top byte of an address is used for address match for the TTBR0_EL1 region, or ignored and used for tagged addresses. Defined values are: |
| TBI1 | Top Byte ignored - indicates whether the top byte of an address is used for address match for the TTBR1_EL1 region, or ignored and used for tagged addresses. Defined values are: |
| TBID0 | When ARMv8.3-PAuth is implemented: Controls the use of the top byte of instruction addresses for address matching. 0 TCR_EL1.TBI0 applies to Instruction and Data accesses. 1 TCR_EL1.TBI0 applies to Data accesses only. This affects addresses where the address would be translated by tables pointed to by TTBR0_EL1. This field resets to an architecturally UNKNOWN value. Otherwise: Reserved, RES0. |
| TBID1 | When ARMv8.3-PAuth is implemented: Controls the use of the top byte of instruction addresses for address matching. 0 TCR_EL1.TBI1 applies to Instruction and Data accesses. 1 TCR_EL1.TBI1 applies to Data accesses only. This affects addresses where the address would be translated by tables pointed to by TTBR1_EL1. This field resets to an architecturally UNKNOWN value. Otherwise: Reserved, RES0. |
| TG0 | Granule size for the TTBR0_EL1. |
| TG1 | Granule size for the TTBR1_EL1. |
Structs
| Register |
Constants
| A1 | |
| AS | |
| EPD0 | |
| EPD1 | |
| IPS | |
| IRGN0 | |
| IRGN1 | |
| ORGN0 | |
| ORGN1 | |
| SH0 | |
| SH1 | |
| T0SZ | |
| T1SZ | |
| TBI0 | |
| TBI1 | |
| TBID0 | |
| TBID1 | |
| TG0 | |
| TG1 |