Module cortex_a::regs::SCTLR_EL2 [−][src]
Modules
| A | Alignment check enable. This is the enable bit for Alignment fault checking at EL2 and, when EL2 is enabled in the current Security state and HCR_EL2.{E2H, TGE} == {1, 1}, EL0. |
| C | Cacheability control, for data accesses. |
| EE | Exception endianness. The possible values are: |
| I | Instruction Cache Control, two possible values: |
| M | MMU enable for EL2 or EL2&0 stage 1 address translation. Possible values of this bit are: |
| SA | SP Alignment check enable. |
| WXN | Force treatment of all memory regions with write permissions as XN. The possible values are: |
Structs
| Register |
Constants
| A | |
| C | |
| EE | |
| I | |
| M | |
| SA | |
| WXN |