Module atsame51j::dmac [−][src]
Expand description
Direct Memory Access Controller
Modules
Active Channel and Levels
Descriptor Memory Section Base Address
Busy Channels
Register block CHANNEL[%s]
CRC Checksum
CRC Control
CRC Data Input
CRC Status
Control
Debug Control
Interrupt Pending
Interrupt Status
Pending Channels
Priority Control 0
Software Trigger Control
Write-Back Memory Section Base Address
Structs
Register block
Register block
Type Definitions
Active Channel and Levels
Descriptor Memory Section Base Address
Busy Channels
CRC Checksum
CRC Control
CRC Data Input
CRC Status
Control
Debug Control
Interrupt Pending
Interrupt Status
Pending Channels
Priority Control 0
Software Trigger Control
Write-Back Memory Section Base Address