[−][src]Module ADuCM302x::i2c0
I2C Master/Slave
Modules
| addr1 | Master Address Byte 1 |
| addr2 | Master Address Byte 2 |
| alt | Hardware General Call ID |
| astretch_scl | Automatic Stretch SCL |
| byt | Start Byte |
| div | Serial Clock Period Divisor |
| id0 | First Slave Address Device ID |
| id1 | Second Slave Address Device ID |
| id2 | Third Slave Address Device ID |
| id3 | Fourth Slave Address Device ID |
| mcrxcnt | Master Current Receive Data Count |
| mctl | Master Control |
| mrx | Master Receive Data |
| mrxcnt | Master Receive Data Count |
| mstat | Master Status |
| mtx | Master Transmit Data |
| sctl | Slave Control |
| shctl | Shared Control |
| srx | Slave Receive |
| sstat | Slave I2C Status/Error/IRQ |
| stat | Master and Slave FIFO Status |
| stx | Slave Transmit |
| tctl | Timing Control Register |
Structs
| RegisterBlock | Register block |
Type Definitions
| ADDR1 | Master Address Byte 1 |
| ADDR2 | Master Address Byte 2 |
| ALT | Hardware General Call ID |
| ASTRETCH_SCL | Automatic Stretch SCL |
| BYT | Start Byte |
| DIV | Serial Clock Period Divisor |
| ID0 | First Slave Address Device ID |
| ID1 | Second Slave Address Device ID |
| ID2 | Third Slave Address Device ID |
| ID3 | Fourth Slave Address Device ID |
| MCRXCNT | Master Current Receive Data Count |
| MCTL | Master Control |
| MRX | Master Receive Data |
| MRXCNT | Master Receive Data Count |
| MSTAT | Master Status |
| MTX | Master Transmit Data |
| SCTL | Slave Control |
| SHCTL | Shared Control |
| SRX | Slave Receive |
| SSTAT | Slave I2C Status/Error/IRQ |
| STAT | Master and Slave FIFO Status |
| STX | Slave Transmit |
| TCTL | Timing Control Register |