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Traps Non-secure EL0 and EL1 accesses to the physical counter register to EL2.
0 From AArch64 state: Non-secure EL0 and EL1 accesses to the CNTPCT_EL0 are trapped to EL2, unless it is trapped by CNTKCTL_EL1.EL0PCTEN.
From AArch32 state: Non-secure EL0 and EL1 accesses to the CNTPCT are trapped to EL2, unless it is trapped by CNTKCTL_EL1.EL0PCTEN or CNTKCTL.PL0PCTEN.
1 This control does not cause any instructions to be trapped.
If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 1 other than for the purpose of a direct read.
Enums
Traps Non-secure EL0 and EL1 accesses to the physical counter register to EL2.