Module cortex_a::regs::SCTLR_EL1 [−][src]
Modules
| A | Alignment check enable. This is the enable bit for Alignment fault checking at EL1 and EL0. |
| C | Cacheability control, for data accesses. |
| I | Instruction access Cacheability control, for accesses at EL0 and EL1: |
| M | MMU enable for EL1 and EL0 stage 1 address translation. Possible values of this bit are: |
| NAA | Non-aligned access. This bit controls generation of Alignment faults at EL1 and EL0 under certain conditions. |
| SA | SP Alignment check enable. |
| SA0 | SP Alignment check enable for EL0. |
Structs
| Register |
Constants
| A | |
| C | |
| I | |
| M | |
| NAA | |
| SA | |
| SA0 |