[−][src]Module cortex_a::regs::SCTLR_EL1::M
MMU enable for EL1 and EL0 stage 1 address translation. Possible values of this bit are:
0 EL1 and EL0 stage 1 address translation disabled.
- See the SCTLR_EL1.I field for the behavior of instruction accesses to Normal memory.
1 EL1 and EL0 stage 1 address translation enabled.
Enums
| Value | MMU enable for EL1 and EL0 stage 1 address translation. Possible values of this bit are: |
Constants
| CLEAR | |
| Disable | |
| Enable | |
| SET |