Module cortex_a::regs::CNTHCTL_EL2::EL1PCEN

Traps Non-secure EL0 and EL1 accesses to the physical timer registers to EL2.

0 From AArch64 state: Non-secure EL0 and EL1 accesses to the CNTP_CTL_EL0, CNTP_CVAL_EL0, and CNTP_TVAL_EL0 are trapped to EL2, unless it is trapped by CNTKCTL_EL1.EL0PTEN.

From AArch32 state: Non-secure EL0 and EL1 accesses to the CNTP_CTL, CNTP_CVAL, and CNTP_TVAL are trapped to EL2, unless it is trapped by CNTKCTL_EL1.EL0PTEN or CNTKCTL.PL0PTEN.

1 This control does not cause any instructions to be trapped.

If EL3 is implemented and EL2 is not implemented, behavior is as if this bit is 1 other than for the purpose of a direct read.

Enums

Value

Traps Non-secure EL0 and EL1 accesses to the physical timer registers to EL2.

Constants

CLEAR
SET