Expand description
Peripheral access API for SSE300 microcontrollers (generated using svd2rust v0.26.0 ( ))
You can find an overview of the generated API here.
API features to be included in the next
// Copyright 2022 Arm Limited and/or its affiliates open-source-office@arm.com // // SPDX-License-Identifier: MIT
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.
Re-exports§
pub use self::syscounter_read as syscounter_read_secure;pub use self::sysinfo as sysinfo_secure;pub use self::timer0 as timer1;pub use self::timer0 as timer2;pub use self::timer0 as timer3;pub use self::timer0 as timer0_secure;pub use self::timer0 as timer1_secure;pub use self::timer0 as timer2_secure;pub use self::timer0 as timer3_secure;pub use self::slowclk as slowclk_secure;pub use self::gpio0 as gpio1;pub use self::gpio0 as gpio2;pub use self::gpio0 as gpio3;pub use self::gpio0 as gpio0_secure;pub use self::gpio0 as gpio1_secure;pub use self::gpio0 as gpio2_secure;pub use self::gpio0 as gpio3_secure;pub use self::dma0 as dma1;pub use self::dma0 as dma2;pub use self::dma0 as dma3;pub use self::dma0 as dma0_secure;pub use self::dma0 as dma1_secure;pub use self::dma0 as dma2_secure;pub use self::dma0 as dma3_secure;pub use self::uart0 as uart1;pub use self::uart0 as uart2;pub use self::uart0 as uart3;pub use self::uart0 as uart4;pub use self::uart0 as uart5;pub use self::uart0 as uart0_secure;pub use self::uart0 as uart1_secure;pub use self::uart0 as uart2_secure;pub use self::uart0 as uart3_secure;pub use self::uart0 as uart4_secure;pub use self::uart0 as uart5_secure;pub use self::i2c0 as i2c1;pub use self::i2c0 as i2c0_secure;pub use self::i2c0 as i2c1_secure;pub use self::ssp0 as ssp1;pub use self::ssp0 as ssp2;pub use self::ssp0 as ssp0_secure;pub use self::ssp0 as ssp1_secure;pub use self::ssp0 as ssp2_secure;pub use self::watchdog as watchdog_secure;pub use self::slowclk as slowclkwatchdog;pub use self::fpgaio as fpgaio_secure;pub use self::scc as scc_secure;pub use self::isram0mpc as isram1mpc;
Modules§
- audio_
i2s - AudioI2S
- dma0
- Direct Memory Access 0 (PL081)
- ethernet
- SMSC LAN9220
- fpgaio
- FPGA System Control I/O
- generic
- Common register and bit access and modify traits
- gpio0
- General-purpose I/O 0
- i2c0
- I2C Touch
- isram0mpc
- ISRAM 0 Memory Protection Controller
- nsacrb
- Non-secure Access Configuration Register Block
- sacrb
- Secure Access Configuration Register Block
- sau
- Security Attribution Unit
- scc
- Serial Communication Controller
- slowclk
- SLOWCLK AON Timer
- ssp0
- SPI 0
- syscontrol
- System Control
- syscounter_
cntrl - System counter control
- syscounter_
read - System counter read
- sysinfo
- System Information
- timer0
- Timer 0
- uart0
- UART 0
- watchdog
- Non-secure Watchdog Timer
Structs§
- AUDIO_
I2S - AudioI2S
- CBP
- Cache and branch predictor maintenance operations
- CPUID
- CPUID
- Core
Peripherals - Core peripherals
- DCB
- Debug Control Block
- DMA0
- Direct Memory Access 0 (PL081)
- DMA0_
SECURE - Direct Memory Access 0 (Secure)
- DMA1
- Direct Memory Access 1
- DMA2
- Direct Memory Access 2
- DMA3
- Direct Memory Access 3
- DMA1_
SECURE - Direct Memory Access 1 (Secure)
- DMA2_
SECURE - Direct Memory Access 2 (Secure)
- DMA3_
SECURE - Direct Memory Access 3 (Secure)
- DWT
- Data Watchpoint and Trace unit
- ETHERNET
- SMSC LAN9220
- FPB
- Flash Patch and Breakpoint unit
- FPGAIO
- FPGA System Control I/O
- FPGAIO_
SECURE - FPGA System Control I/O (Secure)
- FPU
- Floating Point Unit
- GPIO0
- General-purpose I/O 0
- GPIO0_
SECURE - General-purpose I/O 0 (Secure)
- GPIO1
- General-purpose I/O 1
- GPIO2
- General-purpose I/O 2
- GPIO3
- General-purpose I/O 3
- GPIO1_
SECURE - General-purpose I/O 1 (Secure)
- GPIO2_
SECURE - General-purpose I/O 2 (Secure)
- GPIO3_
SECURE - General-purpose I/O 3 (Secure)
- I2C0
- I2C Touch
- I2C0_
SECURE - I2C Touch (Secure)
- I2C1
- I2C Audio
- I2C1_
SECURE - I2C Audio (Secure)
- ISRA
M0MPC - ISRAM 0 Memory Protection Controller
- ISRA
M1MPC - ISRAM 1 Memory Protection Controller
- ITM
- Instrumentation Trace Macrocell
- MPU
- Memory Protection Unit
- NSACRB
- Non-secure Access Configuration Register Block
- NVIC
- Nested Vector Interrupt Controller
- Peripherals
- All the peripherals.
- SACRB
- Secure Access Configuration Register Block
- SAU
- Security Attribution Unit
- SCB
- System Control Block
- SCC
- Serial Communication Controller
- SCC_
SECURE - Serial Communication Controller
- SLOWCLK
- SLOWCLK AON Timer
- SLOWCLKWATCHDOG
- SLOWCLK Watchdog (Secure)
- SLOWCLK_
SECURE - SLOWCLK AON Timer (Secure)
- SSP0
- SPI 0
- SSP0_
SECURE - SPI 0 (Secure)
- SSP1
- SPI 1
- SSP2
- SPI 2
- SSP1_
SECURE - SPI 1 (Secure)
- SSP2_
SECURE - SPI 2 (Secure)
- SYSCONTROL
- System Control
- SYSCOUNTER_
CNTRL - System counter control
- SYSCOUNTER_
READ - System counter read
- SYSCOUNTER_
READ_ SECURE - System Counter Read (Secure)
- SYSINFO
- System Information
- SYSINFO_
SECURE - System Information (Secure)
- SYST
- SysTick: System Timer
- TIMER0
- Timer 0
- TIME
R0_ SECURE - Timer 0 (Secure)
- TIMER1
- Timer 1
- TIMER2
- Timer 2
- TIMER3
- AON Timer 3
- TIME
R1_ SECURE - Timer 1 (Secure)
- TIME
R2_ SECURE - Timer 2 (Secure)
- TIME
R3_ SECURE - Timer 3 (Secure)
- TPIU
- Trace Port Interface Unit
- UART0
- UART 0
- UART0_
SECURE - UART 0 (Secure)
- UART1
- UART 1
- UART2
- UART 2
- UART3
- UART 3
- UART4
- UART 4
- UART5
- UART 5
- UART1_
SECURE - UART 1 (Secure)
- UART2_
SECURE - UART 2 (Secure)
- UART3_
SECURE - UART 3 (Secure)
- UART4_
SECURE - UART 4 (Secure)
- UART5_
SECURE - UART 5 (Secure)
- WATCHDOG
- Non-secure Watchdog Timer
- WATCHDOG_
SECURE - Watchdog (Secure)
Enums§
- Interrupt
- Enumeration of all the interrupts.
Constants§
- NVIC_
PRIO_ BITS - Number available in the NVIC for configuring priority