Crate corstone300_pac

Expand description

Peripheral access API for SSE300 microcontrollers (generated using svd2rust v0.26.0 ( ))

You can find an overview of the generated API here.

API features to be included in the next

svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports

pub use self::syscounter_read as syscounter_read_secure;

pub use self::sysinfo as sysinfo_secure;

pub use self::timer0 as timer1;

pub use self::timer0 as timer2;

pub use self::timer0 as timer3;

pub use self::timer0 as timer0_secure;

pub use self::timer0 as timer1_secure;

pub use self::timer0 as timer2_secure;

pub use self::timer0 as timer3_secure;

pub use self::slowclk as slowclk_secure;

pub use self::gpio0 as gpio1;

pub use self::gpio0 as gpio2;

pub use self::gpio0 as gpio3;

pub use self::gpio0 as gpio0_secure;

pub use self::gpio0 as gpio1_secure;

pub use self::gpio0 as gpio2_secure;

pub use self::gpio0 as gpio3_secure;

pub use self::dma0 as dma1;

pub use self::dma0 as dma2;

pub use self::dma0 as dma3;

pub use self::dma0 as dma0_secure;

pub use self::dma0 as dma1_secure;

pub use self::dma0 as dma2_secure;

pub use self::dma0 as dma3_secure;

pub use self::uart0 as uart1;

pub use self::uart0 as uart2;

pub use self::uart0 as uart3;

pub use self::uart0 as uart4;

pub use self::uart0 as uart5;

pub use self::uart0 as uart0_secure;

pub use self::uart0 as uart1_secure;

pub use self::uart0 as uart2_secure;

pub use self::uart0 as uart3_secure;

pub use self::uart0 as uart4_secure;

pub use self::uart0 as uart5_secure;

pub use self::i2c0 as i2c1;

pub use self::i2c0 as i2c0_secure;

pub use self::i2c0 as i2c1_secure;

pub use self::ssp0 as ssp1;

pub use self::ssp0 as ssp2;

pub use self::ssp0 as ssp0_secure;

pub use self::ssp0 as ssp1_secure;

pub use self::ssp0 as ssp2_secure;

pub use self::watchdog as watchdog_secure;

pub use self::slowclk as slowclkwatchdog;

pub use self::fpgaio as fpgaio_secure;

pub use self::scc as scc_secure;

pub use self::isram0mpc as isram1mpc;

Modules

audio_i2s

AudioI2S

dma0

Direct Memory Access 0 (PL081)

ethernet

SMSC LAN9220

fpgaio

FPGA System Control I/O

generic

Common register and bit access and modify traits

gpio0

General-purpose I/O 0

i2c0

I2C Touch

isram0mpc

ISRAM 0 Memory Protection Controller

nsacrb

Non-secure Access Configuration Register Block

sacrb

Secure Access Configuration Register Block

sau

Security Attribution Unit

scc

Serial Communication Controller

SLOWCLK AON Timer

SPI 0

System Control

System counter control

System counter read

System Information

Timer 0

UART 0

Non-secure Watchdog Timer

Structs

AUDIO_I2S

AudioI2S

CBP

Cache and branch predictor maintenance operations

Core peripherals

Debug Control Block

Direct Memory Access 0 (PL081)

DMA0_SECURE

Direct Memory Access 0 (Secure)

DMA1

Direct Memory Access 1

DMA1_SECURE

Direct Memory Access 1 (Secure)

DMA2

Direct Memory Access 2

DMA2_SECURE

Direct Memory Access 2 (Secure)

DMA3

Direct Memory Access 3

DMA3_SECURE

Direct Memory Access 3 (Secure)

DWT

Data Watchpoint and Trace unit

ETHERNET

SMSC LAN9220

FPB

Flash Patch and Breakpoint unit

FPGAIO

FPGA System Control I/O

FPGAIO_SECURE

FPGA System Control I/O (Secure)

FPU

Floating Point Unit

GPIO0

General-purpose I/O 0

GPIO0_SECURE

General-purpose I/O 0 (Secure)

GPIO1

General-purpose I/O 1

GPIO1_SECURE

General-purpose I/O 1 (Secure)

GPIO2

General-purpose I/O 2

GPIO2_SECURE

General-purpose I/O 2 (Secure)

GPIO3

General-purpose I/O 3

GPIO3_SECURE

General-purpose I/O 3 (Secure)

I2C Touch

I2C Touch (Secure)

I2C Audio

I2C Audio (Secure)

ISRAM 0 Memory Protection Controller

ISRAM1MPC

ISRAM 1 Memory Protection Controller

ITM

Instrumentation Trace Macrocell

MPU

Memory Protection Unit

NSACRB

Non-secure Access Configuration Register Block

NVIC

Nested Vector Interrupt Controller

Peripherals

All the peripherals.

SACRB

Secure Access Configuration Register Block

SAU

Security Attribution Unit

SCB

System Control Block

SCC

Serial Communication Controller

SCC_SECURE

Serial Communication Controller

SLOWCLK

SLOWCLK AON Timer

SLOWCLKWATCHDOG

SLOWCLK Watchdog (Secure)

SLOWCLK_SECURE

SLOWCLK AON Timer (Secure)

SPI 0

SPI 0 (Secure)

SPI 1

SPI 1 (Secure)

SPI 2

SPI 2 (Secure)

System Control

System counter control

SYSCOUNTER_READ

System counter read

SYSCOUNTER_READ_SECURE

System Counter Read (Secure)

SYSINFO

System Information

SYSINFO_SECURE

System Information (Secure)

SYST

SysTick: System Timer

Timer 0

Timer 0 (Secure)

Timer 1

Timer 1 (Secure)

Timer 2

Timer 2 (Secure)

AON Timer 3

Timer 3 (Secure)

Trace Port Interface Unit

UART 0

UART 0 (Secure)

UART 1

UART 1 (Secure)

UART 2

UART 2 (Secure)

UART 3

UART 3 (Secure)

UART 4

UART 4 (Secure)

UART 5

UART 5 (Secure)

Non-secure Watchdog Timer

WATCHDOG_SECURE

Watchdog (Secure)

Enums

Interrupt

Enumeration of all the interrupts.

Constants

NVIC_PRIO_BITS

Number available in the NVIC for configuring priority