1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
use crate::access_ports::{
generic_ap::{GenericAP, IDR},
APRegister,
};
pub trait AccessPort {
fn get_port_number(&self) -> u8;
}
pub trait APAccess<PORT, REGISTER>
where
PORT: AccessPort,
REGISTER: APRegister<PORT>,
{
type Error: std::fmt::Debug;
fn read_register_ap(&mut self, port: PORT, register: REGISTER)
-> Result<REGISTER, Self::Error>;
fn write_register_ap(&mut self, port: PORT, register: REGISTER) -> Result<(), Self::Error>;
}
impl<'a, T, PORT, REGISTER> APAccess<PORT, REGISTER> for &'a mut T
where
T: APAccess<PORT, REGISTER>,
PORT: AccessPort,
REGISTER: APRegister<PORT>,
{
type Error = T::Error;
fn read_register_ap(&mut self, port: PORT, register: REGISTER)
-> Result<REGISTER, Self::Error>
{
(*self).read_register_ap(port, register)
}
fn write_register_ap(&mut self, port: PORT, register: REGISTER) -> Result<(), Self::Error>
{
(*self).write_register_ap(port, register)
}
}
pub fn access_port_is_valid<AP>(debug_port: &mut AP, access_port: GenericAP) -> bool
where
AP: APAccess<GenericAP, IDR>,
{
if let Ok(idr) = debug_port.read_register_ap(access_port, IDR::default()) {
u32::from(idr) != 0
} else {
false
}
}