[][src]Function core_arch::mips::__msa_or_v

pub unsafe fn __msa_or_v(a: v16u8, b: v16u8) -> v16u8
🔬 This is a nightly-only experimental API. (stdsimd)
This is supported on MIPS and target feature msa only.

Vector Logical Or

Each bit of vector 'a'(sixteen unsigned 8-bit integer numbers) is combined with the corresponding bit of vector 'b' (sixteen unsigned 8-bit integer numbers) in a bitwise logical OR operation. The result is written to vector (sixteen unsigned 8-bit integer numbers)