Module ch32v3::ch32v30x::dma1::cfgr5

DMA channel configuration register (DMA_CFGR)

Structs

CFGR5_SPEC

DMA channel configuration register (DMA_CFGR)

R

Register CFGR5 reader

W

Register CFGR5 writer

Type Definitions

CIRC_R

Field CIRC reader - Circular mode

CIRC_W

Field CIRC writer - Circular mode

DIR_R

Field DIR reader - Data transfer direction

DIR_W

Field DIR writer - Data transfer direction

EN_R

Field EN reader - Channel enable

EN_W

Field EN writer - Channel enable

HTIE_R

Field HTIE reader - Half Transfer interrupt enable

HTIE_W

Field HTIE writer - Half Transfer interrupt enable

MEM2MEM_R

Field MEM2MEM reader - Memory to memory mode

MEM2MEM_W

Field MEM2MEM writer - Memory to memory mode

MINC_R

Field MINC reader - Memory increment mode

MINC_W

Field MINC writer - Memory increment mode

MSIZE_R

Field MSIZE reader - Memory size

MSIZE_W

Field MSIZE writer - Memory size

PINC_R

Field PINC reader - Peripheral increment mode

PINC_W

Field PINC writer - Peripheral increment mode

PL_R

Field PL reader - Channel Priority level

PL_W

Field PL writer - Channel Priority level

PSIZE_R

Field PSIZE reader - Peripheral size

PSIZE_W

Field PSIZE writer - Peripheral size

TCIE_R

Field TCIE reader - Transfer complete interrupt enable

TCIE_W

Field TCIE writer - Transfer complete interrupt enable

TEIE_R

Field TEIE reader - Transfer error interrupt enable

TEIE_W

Field TEIE writer - Transfer error interrupt enable