Crate cec1736_pac
source · [−]Expand description
Peripheral access API for CEC1736_S0_2HW microcontrollers (generated using svd2rust v0.25.1 ( ))
You can find an overview of the generated API here.
API features to be included in the next
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.
Re-exports
pub use self::Interrupt as interrupt;pub use dma_chan02 as dma_chan03;pub use dma_chan02 as dma_chan04;pub use dma_chan02 as dma_chan05;pub use dma_chan02 as dma_chan06;pub use dma_chan02 as dma_chan07;pub use dma_chan02 as dma_chan08;pub use dma_chan02 as dma_chan09;pub use timer32_0 as timer32_1;pub use htm0 as htm1;pub use led0 as led1;pub use smb0 as smb1;pub use smb0 as smb2;pub use smb0 as smb3;pub use smb0 as smb4;pub use spt0 as spt1;pub use spi_mon0 as spi_mon1;Modules
This is a 16-bit auto-reloading timer/counter.
DMA Channel 00 Registers
DMA Channel 01 Registers
DMA Channel 02 Registers
DMA Main Registers
This block is designed to be accessed internally by the EC via the register interface.
The ECIA works in conjunction with the processor interrupt interface to handle hardware interrupts andd exceptions.
Environmental Monitor Block
The Logical Device Configuration registers support motherboard designs in which the resources required by their components are known and assigned by the BIOS at POST.
Common register and bit access and modify traits
GPIO Pin Control Registers
The Hibernation Timer can generate a wake event to the Embedded Controller (EC) when it is in a hibernation mode.
Internal Master SPI.
The LED is implemented using a PWM that can be driven either by the 48 MHz clock or by a 32.768 KHz clock input.
OTP Programming registers.
The Power, Clocks, and Resets (PCR) Section identifies clock sources, and reset inputs to the chip.
The PWM block generates an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz.
The QMSPI may be used to communicate with various peripheral devices that use a Serial Peripheral Interface.
RTOS is a 32-bit timer designed to operate on the 32kHz oscillator which is available during all chip sleep states.
The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
SPI Monitor Block
SPI Peripheral Target Register.
System timer
System Control Registers
The TFDP serially transmits EC-originated diagnostic vectors to an external debug trace system.
This 32-bit timer block offers a simple mechanism for firmware to maintain a time base.
The 16550 UART is a full-function Two Pin Serial Port that supports the standard RS-232 Interface.
The VBAT Register Bank block is a block implemented for miscellaneous battery-backed registers.
The function of the Watchdog Timer is to provide a mechanism to detect if the internal embedded controller has failed.
Structs
Cache and branch predictor maintenance operations
This is a 16-bit auto-reloading timer/counter.
CPUID
Core peripherals
Debug Control Block
DMA Channel 00 Registers
DMA Channel 01 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Main Registers
Data Watchpoint and Trace unit
The ECIA works in conjunction with the processor interrupt interface to handle hardware interrupts andd exceptions.
This block is designed to be accessed internally by the EC via the register interface.
Environmental Monitor Block
Flash Patch and Breakpoint unit
Floating Point Unit
The Logical Device Configuration registers support motherboard designs in which the resources required by their components are known and assigned by the BIOS at POST.
GPIO Pin Control Registers
The Hibernation Timer can generate a wake event to the Embedded Controller (EC) when it is in a hibernation mode.
The Hibernation Timer can generate a wake event to the Embedded Controller (EC) when it is in a hibernation mode.
Internal Master SPI.
Instrumentation Trace Macrocell
The LED is implemented using a PWM that can be driven either by the 48 MHz clock or by a 32.768 KHz clock input.
The LED is implemented using a PWM that can be driven either by the 48 MHz clock or by a 32.768 KHz clock input.
Memory Protection Unit
Nested Vector Interrupt Controller
OTP Programming registers.
The Power, Clocks, and Resets (PCR) Section identifies clock sources, and reset inputs to the chip.
The PWM block generates an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz.
All the peripherals
The QMSPI may be used to communicate with various peripheral devices that use a Serial Peripheral Interface.
RTOS is a 32-bit timer designed to operate on the 32kHz oscillator which is available during all chip sleep states.
System Control Block
The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
SPI Monitor Block
SPI Monitor Block
SPI Peripheral Target Register.
SPI Peripheral Target Register.
SysTick: System Timer
System Control Registers
System timer
The TFDP serially transmits EC-originated diagnostic vectors to an external debug trace system.
This 32-bit timer block offers a simple mechanism for firmware to maintain a time base.
This 32-bit timer block offers a simple mechanism for firmware to maintain a time base.
Trace Port Interface Unit
The 16550 UART is a full-function Two Pin Serial Port that supports the standard RS-232 Interface.
The VBAT Register Bank block is a block implemented for miscellaneous battery-backed registers.
The function of the Watchdog Timer is to provide a mechanism to detect if the internal embedded controller has failed.
Enums
Enumeration of all the interrupts.
Constants
Number available in the NVIC for configuring priority