Crate cec1712_pac
source · [−]Expand description
Peripheral access API for CEC1712H_B2_SX microcontrollers (generated using svd2rust v0.25.1 ( ))
You can find an overview of the generated API here.
API features to be included in the next
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.
Re-exports
pub use self::Interrupt as interrupt;pub use dma_chan02 as dma_chan03;pub use dma_chan02 as dma_chan04;pub use dma_chan02 as dma_chan05;pub use dma_chan02 as dma_chan06;pub use dma_chan02 as dma_chan07;pub use dma_chan02 as dma_chan08;pub use dma_chan02 as dma_chan09;pub use dma_chan02 as dma_chan10;pub use dma_chan02 as dma_chan11;pub use uart0 as uart1;pub use uart0 as uart2;pub use timer16_0 as timer16_1;pub use timer32_0 as timer32_1;pub use htm0 as htm1;pub use tach0 as tach1;pub use pwm0 as pwm2;pub use pwm0 as pwm3;pub use pwm0 as pwm5;pub use pwm0 as pwm6;pub use pwm0 as pwm7;pub use led0 as led1;pub use smb0 as smb1;pub use smb0 as smb2;pub use smb0 as smb3;pub use smb0 as smb4;pub use i2c0 as i2c1;pub use i2c0 as i2c2;Modules
This block is designed to convert external analog voltage readings into digital values.
This is a 16-bit auto-reloading timer/counter.
DMA Channel 00 Registers
DMA Channel 01 Registers
DMA Channel 02 Registers
DMA Main Registers
This block is designed to be accessed internally by the EC via the register interface.
The ECIA works in conjunction with the processor interrupt interface to handle hardware interrupts andd exceptions.
The Logical Device Configuration registers support motherboard designs in which the resources required by their components are known and assigned by the BIOS at POST.
Common register and bit access and modify traits
GPIO Pin Control Registers
The Hibernation Timer can generate a wake event to the Embedded Controller (EC) when it is in a hibernation mode
The I2C interface can handle standard I2C interface.
The LED is implemented using a PWM that can be driven either by the 48 MHz clock or by a 32.768 KHz clock input.
The Power, Clocks, and Resets (PCR) Section identifies clock sources, and reset inputs to the chip
The PWM block generates an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz
The QMSPI may be used to communicate with various peripheral devices that use a Serial Peripheral Interface
This is the set of registers that are automatically counted by hardware every 1 second while the block is enabled
RTOS is a 32-bit timer designed to operate on the 32kHz oscillator which is available during all chip sleep states.
The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
System timer
System Control Registers
This block monitors TACH output signals from various types of fans, and determines their speed.
The TFDP serially transmits EC-originated diagnostic vectors to an external debug trace system.
This 16-bit timer block offers a simple mechanism for firmware to maintain a time base
This 32-bit timer block offers a simple mechanism for firmware to maintain a time base
The 16550 UART is a full-function Two Pin Serial Port that supports the standard RS-232 Interface.
The VBAT Register Bank block is a block implemented for miscellaneous battery-backed registers
The VBAT RAM is operational while the main power rail is operational, and will retain its values powered by battery power while the main rail is unpowered.
The VBAT-Powered Control Interfaces with the RTC With Date and DST Adjustment as well as the Week Alarm.
The function of the Watchdog Timer is to provide a mechanism to detect if the internal embedded controller has failed.
The Week Timer and the Sub-Week Timer assert the Power-Up Event Output which automatically powers-up the system from the G3 state
Structs
This block is designed to convert external analog voltage readings into digital values.
Cache and branch predictor maintenance operations
This is a 16-bit auto-reloading timer/counter.
CPUID
Core peripherals
Debug Control Block
DMA Channel 00 Registers
DMA Channel 01 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Channel 02 Registers
DMA Main Registers
Data Watchpoint and Trace unit
The ECIA works in conjunction with the processor interrupt interface to handle hardware interrupts andd exceptions.
This block is designed to be accessed internally by the EC via the register interface.
Flash Patch and Breakpoint unit
The Logical Device Configuration registers support motherboard designs in which the resources required by their components are known and assigned by the BIOS at POST.
GPIO Pin Control Registers
The Hibernation Timer can generate a wake event to the Embedded Controller (EC) when it is in a hibernation mode
The Hibernation Timer can generate a wake event to the Embedded Controller (EC) when it is in a hibernation mode
The I2C interface can handle standard I2C interface.
The I2C interface can handle standard I2C interface.
The I2C interface can handle standard I2C interface.
Instrumentation Trace Macrocell
The LED is implemented using a PWM that can be driven either by the 48 MHz clock or by a 32.768 KHz clock input.
The LED is implemented using a PWM that can be driven either by the 48 MHz clock or by a 32.768 KHz clock input.
Memory Protection Unit
Nested Vector Interrupt Controller
The Power, Clocks, and Resets (PCR) Section identifies clock sources, and reset inputs to the chip
The PWM block generates an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz
The PWM block generates an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz
The PWM block generates an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz
The PWM block generates an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz
The PWM block generates an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz
The PWM block generates an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz
All the peripherals
The QMSPI may be used to communicate with various peripheral devices that use a Serial Peripheral Interface
This is the set of registers that are automatically counted by hardware every 1 second while the block is enabled
RTOS is a 32-bit timer designed to operate on the 32kHz oscillator which is available during all chip sleep states.
System Control Block
The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
The SMBus interface can handle standard SMBus 2.0 protocols as well as I2C interface.
SysTick: System Timer
System Control Registers
System timer
This block monitors TACH output signals from various types of fans, and determines their speed.
This block monitors TACH output signals from various types of fans, and determines their speed.
The TFDP serially transmits EC-originated diagnostic vectors to an external debug trace system.
This 16-bit timer block offers a simple mechanism for firmware to maintain a time base
This 16-bit timer block offers a simple mechanism for firmware to maintain a time base
This 32-bit timer block offers a simple mechanism for firmware to maintain a time base
This 32-bit timer block offers a simple mechanism for firmware to maintain a time base
Trace Port Interface Unit
The 16550 UART is a full-function Two Pin Serial Port that supports the standard RS-232 Interface.
The 16550 UART is a full-function Two Pin Serial Port that supports the standard RS-232 Interface.
The 16550 UART is a full-function Two Pin Serial Port that supports the standard RS-232 Interface.
The VBAT Register Bank block is a block implemented for miscellaneous battery-backed registers
The VBAT RAM is operational while the main power rail is operational, and will retain its values powered by battery power while the main rail is unpowered.
The VBAT-Powered Control Interfaces with the RTC With Date and DST Adjustment as well as the Week Alarm.
The function of the Watchdog Timer is to provide a mechanism to detect if the internal embedded controller has failed.
The Week Timer and the Sub-Week Timer assert the Power-Up Event Output which automatically powers-up the system from the G3 state
Enums
Enumeration of all the interrupts.
Constants
Number available in the NVIC for configuring priority