Module cc3220sf::gpioa0::mis

0x4000 5418 0x4000 6418 0x4000 7418 0x4002 4418 GPIO Masked Interrupt Status (GPIOMIS)@@ offset 0x418 The GPIOMIS register is the masked interrupt status register. If a bit is set in this register@@ the corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear@@ either no interrupt has been generated@@ or the interrupt is masked. If no port pin@@ other than the one that is being used as an ADC trigger@@ is being used to generate interrupts@@ the appropriate Interrupt Set Enable (ENn) register can disable the interrupts for the port@@ and the ADC interrupt can be used to read back the converted data. Otherwise@@ the port interrupt handler must ignore and clear interrupts on the port pin and wait for the ADC interrupt@@ or the ADC interrupt must be disabled in the EN0 register and the port interrupt handler must poll the ADC registers until the conversion is completed. If no port pin@@ other than the one that is being used as an ADC trigger@@ is being used to generate interrupts@@ the appropriate Interrupt Set Enable (ENn) register can disable the interrupts for the port@@ and the ADC interrupt can be used to read back the converted data. Otherwise@@ the port interrupt handler must ignore and clear interrupts on the port pin and wait for the ADC interrupt@@ or the ADC interrupt must be disabled in the EN0 register and the port interrupt handler must poll the ADC registers until the conversion is completed. Note that if the Port B GPIOADCCTL register is cleared@@ PB4 can still be used as an external trigger for the ADC. This is a legacy mode which allows code written for previous Stellaris devices to operate on this microcontroller. GPIOMIS is the state of the interrupt after masking.

Type Definitions

R	Reader of register MIS
W	Writer for register MIS