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#[doc = "Reader of register UART0CLKEN"] pub type R = crate::R<u32, super::UART0CLKEN>; #[doc = "Writer for register UART0CLKEN"] pub type W = crate::W<u32, super::UART0CLKEN>; #[doc = "Register UART0CLKEN `reset()`'s with value 0"] impl crate::ResetValue for super::UART0CLKEN { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `UART0DSLPCLKEN`"] pub type UART0DSLPCLKEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `UART0DSLPCLKEN`"] pub struct UART0DSLPCLKEN_W<'a> { w: &'a mut W, } impl<'a> UART0DSLPCLKEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); self.w } } #[doc = "Reader of field `NU1`"] pub type NU1_R = crate::R<u8, u8>; #[doc = "Reader of field `UART0SLPCLKEN`"] pub type UART0SLPCLKEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `UART0SLPCLKEN`"] pub struct UART0SLPCLKEN_W<'a> { w: &'a mut W, } impl<'a> UART0SLPCLKEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); self.w } } #[doc = "Reader of field `NU2`"] pub type NU2_R = crate::R<u8, u8>; #[doc = "Reader of field `UART0RCLKEN`"] pub type UART0RCLKEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `UART0RCLKEN`"] pub struct UART0RCLKEN_W<'a> { w: &'a mut W, } impl<'a> UART0RCLKEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } impl R { #[doc = "Bit 16 - UART_A0_DSLP_CLK_ENABLE"] #[inline(always)] pub fn uart0dslpclken(&self) -> UART0DSLPCLKEN_R { UART0DSLPCLKEN_R::new(((self.bits >> 16) & 0x01) != 0) } #[doc = "Bits 9:15 - NU1"] #[inline(always)] pub fn nu1(&self) -> NU1_R { NU1_R::new(((self.bits >> 9) & 0x7f) as u8) } #[doc = "Bit 8 - UART_A0_SLP_CLK_ENABLE"] #[inline(always)] pub fn uart0slpclken(&self) -> UART0SLPCLKEN_R { UART0SLPCLKEN_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bits 1:7 - NU2"] #[inline(always)] pub fn nu2(&self) -> NU2_R { NU2_R::new(((self.bits >> 1) & 0x7f) as u8) } #[doc = "Bit 0 - UART_A0_RUN_CLK_ENABLE"] #[inline(always)] pub fn uart0rclken(&self) -> UART0RCLKEN_R { UART0RCLKEN_R::new((self.bits & 0x01) != 0) } } impl W { #[doc = "Bit 16 - UART_A0_DSLP_CLK_ENABLE"] #[inline(always)] pub fn uart0dslpclken(&mut self) -> UART0DSLPCLKEN_W { UART0DSLPCLKEN_W { w: self } } #[doc = "Bit 8 - UART_A0_SLP_CLK_ENABLE"] #[inline(always)] pub fn uart0slpclken(&mut self) -> UART0SLPCLKEN_W { UART0SLPCLKEN_W { w: self } } #[doc = "Bit 0 - UART_A0_RUN_CLK_ENABLE"] #[inline(always)] pub fn uart0rclken(&mut self) -> UART0RCLKEN_W { UART0RCLKEN_W { w: self } } }