Module cc3220sf::stackdie_ctrl

STACKDIE_CTRL

Modules

base_up_acc_req_bk2	In Spinlock mode whenever Base processor wants the access to Sram Bank2 it should request for it by writing into this register. It'll get interrupt whenever it is granted. In Handshake mode this bit will be set by Stack processor. Its a set only bit and is cleared by HW when the request is granted.
base_up_acc_req_bk3	In Spinlock mode whenever Base processor wants the access to Sram Bank3 it should request for it by writing into this register. It'll get interrupt whenever it is granted. In Handshake mode this bit will be set by Stack processor. Its a set only bit and is cleared by HW when the request is granted.
base_up_irq_log	Reading this register Base procesor will able to know the reason for the interrupt. This is clear only register - set by HW upon an interrupt to Base processor and can be cleared only by BASE processor.
bus_fault_addr	Stores the last bus fault address.
bus_fault_clr	write only registers on read returns 0.W Write 1 to clear the bust fault to store the new bus fault address
dma_req	To send Dma Request to bottom die.
fmc_sleep_ctl	By posting the request Flash can be put into low-power mode (Sleep) without powering down the Flash. Earlier (in Garnet) this was fully h/w controlled and the control for this was coming from SysCtl while entering into Cortex Deep-sleep mode. But for our device the D2D i/f doesnt support this. The Firmware has to program the register in the top-die for entering into this mode and wait for an interrupt.
misc_ctl	Miscellanious control register.
padn_ctl_0	Mainly for For controlling the pads OEN pins. There are total 60 pads and hence 60 control registe i.e n value varies from 0 to 59. Here is the mapping for the pad_ctl register number and the functionality : 0 D2DPAD_DMAREQ1 1 D2DPAD_DMAREQ0 2 D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4 D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6 D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8 D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS 10 D2DPAD_JTAG_TDI 11-27 D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE -1:0] 28-56 D2DPAD_TOSTACK [D2D_TOSTACK_SIZE -1:0] 57-59 D2DPAD_SPARE [D2D_SPARE_PAD_SIZE -1:0] 0:00 ****************************************************************************
rdsm_cfg_cpu	Read State Machine timing configuration register. Generally Bit 4 and 3 will be identical. For stacked die always 43 are 0 and 6:5 == 1 for 120Mhz.
rdsm_cfg_ee	Read State Machine timing configuration register. Generally Bit 4 and 3 will be identical. For stacked die always 43 are 0 and 6:5 == 1 for 120Mhz.
reset_cause	Reset cause value captured from the ICR_CLKRST block.
spin_lock_mode	Can be written only by the base processor. Decides the ram sharing mode :: handshake or Spinlock mode.
sr_master_priority	This register defines who among base processor and stack processor have highest priority for Sram Access. Can be written only by Base Processor.
sram_jump_offset_addr	Address offset within SRAM to which CM3 should jump after reset.
stk_clk_en	Can be written only by base processor. Controls the enable pin of the cgcs for the clocks going to CM3 dft ctrl block and Sram.
stk_sr_acc_ctl_bk2	In Spinlock mode this Register defines who among base processor and stack processor have access to Sram Bank2 right now. In Handshake mode this Register defines who among base processor and stack processor have access to Sram Bank2 and Bank3 right now. Its Clear only register and is set by hardware. Lower bit can be cleared only by Base Processor and Upper bit Cleared only by the Stack processor.
stk_sr_acc_ctl_bk3	Register defines who among base processor and stack processor have access to Sram Bank3 right now. Its Clear only register and is set by hardware. Lower bit can be cleared only by Base Processor and Upper bit Cleared only by the Stack processor.
stk_up_acc_req_bk2	In Spinlock mode Whenever Stack processor wants the access to Sram Bank2 it should request for it by writing into this register. It'll get interrupt whenever it is granted. In Handshake mode this bit will be set by the Base processor. Its a set only bit and is cleared by HW when the request is granted.
stk_up_acc_req_bk3	In Spinlock mode Whenever Stack processor wants the access to Sram Bank3 it should request for it by writing into this register. It'll get interrupt whenever it is granted. In Handshake mode this bit will be set by the Base processor. Its a set only bit and is cleared by HW when the request is granted.
stk_up_irq_log	Reading this register Stack procesor will able to know the reason for the interrupt. This is clear only register - set by HW upon an interrupt to Stack processor and can be cleared only by Stack processor.
stk_up_reset	Can be written only by Base Processor. Writing to this register will reset the stack processor reset will be de-asserted upon clearing this register.
sw_dft_ctl	DFT control and status bits
sw_reg1	These are sw registers for topdie processor and bottom die processor to communicate. Both can set and read these registers. In case of write clash bottom die's processor wins and top die processor access is ignored.
sw_reg2	These are sw registers for topdie processor and bottom die processor to communicate. Both can set and read these registers. In case of write clash bottom die's processor wins and top die processor access is ignored.
wdog_timer_event	Watchdog timer event value captured from the ICR_CLKRST block

Structs

RegisterBlock

Register block

Type Definitions

BASE_UP_ACC_REQ_BK2	In Spinlock mode whenever Base processor wants the access to Sram Bank2 it should request for it by writing into this register. It'll get interrupt whenever it is granted. In Handshake mode this bit will be set by Stack processor. Its a set only bit and is cleared by HW when the request is granted.
BASE_UP_ACC_REQ_BK3	In Spinlock mode whenever Base processor wants the access to Sram Bank3 it should request for it by writing into this register. It'll get interrupt whenever it is granted. In Handshake mode this bit will be set by Stack processor. Its a set only bit and is cleared by HW when the request is granted.
BASE_UP_IRQ_LOG	Reading this register Base procesor will able to know the reason for the interrupt. This is clear only register - set by HW upon an interrupt to Base processor and can be cleared only by BASE processor.
BUS_FAULT_ADDR	Stores the last bus fault address.
BUS_FAULT_CLR	write only registers on read returns 0.W Write 1 to clear the bust fault to store the new bus fault address
DMA_REQ	To send Dma Request to bottom die.
FMC_SLEEP_CTL	By posting the request Flash can be put into low-power mode (Sleep) without powering down the Flash. Earlier (in Garnet) this was fully h/w controlled and the control for this was coming from SysCtl while entering into Cortex Deep-sleep mode. But for our device the D2D i/f doesnt support this. The Firmware has to program the register in the top-die for entering into this mode and wait for an interrupt.
MISC_CTL	Miscellanious control register.
PADN_CTL_0	Mainly for For controlling the pads OEN pins. There are total 60 pads and hence 60 control registe i.e n value varies from 0 to 59. Here is the mapping for the pad_ctl register number and the functionality : 0 D2DPAD_DMAREQ1 1 D2DPAD_DMAREQ0 2 D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4 D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6 D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8 D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS 10 D2DPAD_JTAG_TDI 11-27 D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE -1:0] 28-56 D2DPAD_TOSTACK [D2D_TOSTACK_SIZE -1:0] 57-59 D2DPAD_SPARE [D2D_SPARE_PAD_SIZE -1:0] 0:00 ****************************************************************************
RDSM_CFG_CPU	Read State Machine timing configuration register. Generally Bit 4 and 3 will be identical. For stacked die always 43 are 0 and 6:5 == 1 for 120Mhz.
RDSM_CFG_EE	Read State Machine timing configuration register. Generally Bit 4 and 3 will be identical. For stacked die always 43 are 0 and 6:5 == 1 for 120Mhz.
RESET_CAUSE	Reset cause value captured from the ICR_CLKRST block.
SPIN_LOCK_MODE	Can be written only by the base processor. Decides the ram sharing mode :: handshake or Spinlock mode.
SRAM_JUMP_OFFSET_ADDR	Address offset within SRAM to which CM3 should jump after reset.
SR_MASTER_PRIORITY	This register defines who among base processor and stack processor have highest priority for Sram Access. Can be written only by Base Processor.
STK_CLK_EN	Can be written only by base processor. Controls the enable pin of the cgcs for the clocks going to CM3 dft ctrl block and Sram.
STK_SR_ACC_CTL_BK2	In Spinlock mode this Register defines who among base processor and stack processor have access to Sram Bank2 right now. In Handshake mode this Register defines who among base processor and stack processor have access to Sram Bank2 and Bank3 right now. Its Clear only register and is set by hardware. Lower bit can be cleared only by Base Processor and Upper bit Cleared only by the Stack processor.
STK_SR_ACC_CTL_BK3	Register defines who among base processor and stack processor have access to Sram Bank3 right now. Its Clear only register and is set by hardware. Lower bit can be cleared only by Base Processor and Upper bit Cleared only by the Stack processor.
STK_UP_ACC_REQ_BK2	In Spinlock mode Whenever Stack processor wants the access to Sram Bank2 it should request for it by writing into this register. It'll get interrupt whenever it is granted. In Handshake mode this bit will be set by the Base processor. Its a set only bit and is cleared by HW when the request is granted.
STK_UP_ACC_REQ_BK3	In Spinlock mode Whenever Stack processor wants the access to Sram Bank3 it should request for it by writing into this register. It'll get interrupt whenever it is granted. In Handshake mode this bit will be set by the Base processor. Its a set only bit and is cleared by HW when the request is granted.
STK_UP_IRQ_LOG	Reading this register Stack procesor will able to know the reason for the interrupt. This is clear only register - set by HW upon an interrupt to Stack processor and can be cleared only by Stack processor.
STK_UP_RESET	Can be written only by Base Processor. Writing to this register will reset the stack processor reset will be de-asserted upon clearing this register.
SW_DFT_CTL	DFT control and status bits
SW_REG1	These are sw registers for topdie processor and bottom die processor to communicate. Both can set and read these registers. In case of write clash bottom die's processor wins and top die processor access is ignored.
SW_REG2	These are sw registers for topdie processor and bottom die processor to communicate. Both can set and read these registers. In case of write clash bottom die's processor wins and top die processor access is ignored.
WDOG_TIMER_EVENT	Watchdog timer event value captured from the ICR_CLKRST block