Module cc3220sf::sspi

SSPI

Modules

ch0conf	0x4402 112C 0x4402 212C This register is dedicated to the configuration of the channel 0
ch0stat	0x4402 1130 0x4402 2130 This register provides status information about transmitter and receiver registers of channel 0
ch0ctrl	0x4402 1134 0x4402 2134 This register is dedicated to enable the channel 0
ch1conf	0x4402 1140 0x4402 2140 This register is dedicated to the configuration of the channel.
ch1stat	0x4402 1144 0x4402 2144 This register provides status information about transmitter and receiver registers of channel 1
ch1ctrl	0x4402 1148 0x4402 2148 This register is dedicated to enable the channel 1
ch2conf	0x4402 1154 0x4402 2154 This register is dedicated to the configuration of the channel 2
ch2stat	0x4402 1158 0x4402 2158 This register provides status information about transmitter and receiver registers of channel 2
ch2ctrl	0x4402 115C 0x4402 215C This register is dedicated to enable the channel 2
ch3conf	0x4402 1168 0x4402 2168 This register is dedicated to the configuration of the channel 3
ch3stat	0x4402 116C 0x4402 216C This register provides status information about transmitter and receiver registers of channel 3
ch3ctrl	0x4402 1170 0x4402 2170 This register is dedicated to enable the channel 3
dafrx	0x4402 11A0 0x4402 21A0 This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled. ****************************************************************************
daftx	0x4402 1180 0x4402 2180 This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled.
hl_hwinfo	Information about the IP module's hardware configuration i.e. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide.
hl_rev	IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility
hl_sysconfig	0x4402 1010 0x4402 2010 Clock management configuration
irqenable	0x4402 111C 0x4402 211C This register allows to enable/disable the module internal sources of interrupt on an event-by-event basis.
irqstatus	0x4402 1118 0x4402 2118 The interrupt status regroups all the status of the module internal events that can generate an interrupt
modulctrl	0x4402 1128 0x4402 2128 This register is dedicated to the configuration of the serial port interface.
revision	0x4402 1100 0x4402 2100 This register contains the hard coded RTL revision number.
rx0	0x4402 113C 0x4402 213C This register contains a single SPI word received through the serial link what ever SPI word length is.
rx1	0x4402 1150 0x4402 2150 This register contains a single SPI word received through the serial link what ever SPI word length is.
rx2	0x4402 1164 0x4402 2164 This register contains a single SPI word received through the serial link what ever SPI word length is.
rx3	0x4402 1178 0x4402 2178 This register contains a single SPI word received through the serial link what ever SPI word length is.
sysconfig	0x4402 1110 0x4402 2110 This register allows controlling various parameters of the OCP interface.
sysstatus	0x4402 1114 0x4402 2114 This register provides status information about the module excluding the interrupt status information
syst	0x4402 1124 0x4402 2124 This register is used to check the correctness of the system interconnect either internally to peripheral bus or externally to device IO pads when the module is configured in system test (SYSTEST) mode.
tx0	0x4402 1138 0x4402 2138 This register contains a single SPI word to transmit on the serial link what ever SPI word length is.
tx1	0x4402 114C 0x4402 214C This register contains a single SPI word to transmit on the serial link what ever SPI word length is.
tx2	0x4402 1160 0x4402 2160 This register contains a single SPI word to transmit on the serial link what ever SPI word length is.
tx3	0x4402 1174 0x4402 2174 This register contains a single SPI word to transmit on the serial link what ever SPI word length is.
wakeupenable	0x4402 1120 0x4402 2120 The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis.
xferlevel	0x4402 117C 0x4402 217C This register provides transfer levels needed while using FIFO buffer during transfer.

Structs

RegisterBlock

Register block

Type Definitions

CH0CONF	0x4402 112C 0x4402 212C This register is dedicated to the configuration of the channel 0
CH0STAT	0x4402 1130 0x4402 2130 This register provides status information about transmitter and receiver registers of channel 0
CH0CTRL	0x4402 1134 0x4402 2134 This register is dedicated to enable the channel 0
CH1CONF	0x4402 1140 0x4402 2140 This register is dedicated to the configuration of the channel.
CH1STAT	0x4402 1144 0x4402 2144 This register provides status information about transmitter and receiver registers of channel 1
CH1CTRL	0x4402 1148 0x4402 2148 This register is dedicated to enable the channel 1
CH2CONF	0x4402 1154 0x4402 2154 This register is dedicated to the configuration of the channel 2
CH2STAT	0x4402 1158 0x4402 2158 This register provides status information about transmitter and receiver registers of channel 2
CH2CTRL	0x4402 115C 0x4402 215C This register is dedicated to enable the channel 2
CH3CONF	0x4402 1168 0x4402 2168 This register is dedicated to the configuration of the channel 3
CH3STAT	0x4402 116C 0x4402 216C This register provides status information about transmitter and receiver registers of channel 3
CH3CTRL	0x4402 1170 0x4402 2170 This register is dedicated to enable the channel 3
DAFRX	0x4402 11A0 0x4402 21A0 This register contains the SPI words to received on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_RX(i) register corresponding to the channel which have its FIFO enabled. ****************************************************************************
DAFTX	0x4402 1180 0x4402 2180 This register contains the SPI words to transmit on the serial link when FIFO used and DMA address is aligned on 256 bit.This register is an image of one of MCSPI_TX(i) register corresponding to the channel which have its FIFO enabled.
HL_HWINFO	Information about the IP module's hardware configuration i.e. typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide.
HL_REV	IP Revision Identifier (X.Y.R) Used by software to track features bugs and compatibility
HL_SYSCONFIG	0x4402 1010 0x4402 2010 Clock management configuration
IRQENABLE	0x4402 111C 0x4402 211C This register allows to enable/disable the module internal sources of interrupt on an event-by-event basis.
IRQSTATUS	0x4402 1118 0x4402 2118 The interrupt status regroups all the status of the module internal events that can generate an interrupt
MODULCTRL	0x4402 1128 0x4402 2128 This register is dedicated to the configuration of the serial port interface.
REVISION	0x4402 1100 0x4402 2100 This register contains the hard coded RTL revision number.
RX0	0x4402 113C 0x4402 213C This register contains a single SPI word received through the serial link what ever SPI word length is.
RX1	0x4402 1150 0x4402 2150 This register contains a single SPI word received through the serial link what ever SPI word length is.
RX2	0x4402 1164 0x4402 2164 This register contains a single SPI word received through the serial link what ever SPI word length is.
RX3	0x4402 1178 0x4402 2178 This register contains a single SPI word received through the serial link what ever SPI word length is.
SYSCONFIG	0x4402 1110 0x4402 2110 This register allows controlling various parameters of the OCP interface.
SYSSTATUS	0x4402 1114 0x4402 2114 This register provides status information about the module excluding the interrupt status information
SYST	0x4402 1124 0x4402 2124 This register is used to check the correctness of the system interconnect either internally to peripheral bus or externally to device IO pads when the module is configured in system test (SYSTEST) mode.
TX0	0x4402 1138 0x4402 2138 This register contains a single SPI word to transmit on the serial link what ever SPI word length is.
TX1	0x4402 114C 0x4402 214C This register contains a single SPI word to transmit on the serial link what ever SPI word length is.
TX2	0x4402 1160 0x4402 2160 This register contains a single SPI word to transmit on the serial link what ever SPI word length is.
TX3	0x4402 1174 0x4402 2174 This register contains a single SPI word to transmit on the serial link what ever SPI word length is.
WAKEUPENABLE	0x4402 1120 0x4402 2120 The wakeup enable register allows to enable/disable the module internal sources of wakeup on event-by-event basis.
XFERLEVEL	0x4402 117C 0x4402 217C This register provides transfer levels needed while using FIFO buffer during transfer.