Module cc3220sf::shamd5

SHAMD5

Modules

data0_in	Data input message 0
data1_in	Data input message 1
data2_in	Data input message 2
data3_in	Data input message 3
data4_in	Data input message 4
data5_in	Data input message 5
data6_in	Data input message 6
data7_in	Data input message 7
data8_in	Data input message 8
data9_in	Data input message 9
data10_in	Data input message 10
data11_in	Data input message 11
data12_in	Data input message 12
data13_in	Data input message 13
data14_in	Data input message 14
data15_in	Data input message 15
digest_count	WRITE: Initial Digest Count ([31:6] only [5:0] assumed 0) READ: Result / IntermediateDigest Count The initial digest byte count for hash/HMAC continue operations (HMAC Key Processing = 0 and Use Algorithm Constants = 0) on the Secure World must be written to this register prior to starting the operation by writing to S_HASH_MODE. When either HMAC Key Processing is 1 or Use Algorithm Constants is 1 this register does not need to be written it will be overwritten with 64 (1 hash block of key XOR ipad) or 0 respectively automatically. When starting a HMAC operation from pre-computes (HMAC Key Processing is 0) then the value 64 must be written here to compensate for the appended key XOR ipad block. Note that the value written should always be a 64 byte multiple the lower 6 bits written are ignored. The updated digest byte count (initial digest byte count + bytes processed) can be read from this register when the status register indicates that the operation is done or suspended due to a context switch request or when a Secure World context out DMA is requested. In Advanced DMA mode when not suspended with a partial result reading the SHAMD5_DIGEST_COUNT register triggers the Hash/HMAC Engine to start the next context input DMA. Therefore reading the SHAMD5_DIGEST_COUNT register should always be the last context-read action if not suspended with a partial result (i.e. PartHashReady interrupt not pending).
hash512_odigest_a	HASH512_ODIGEST_A
hash512_odigest_b	HASH512_ODIGEST_B
hash512_odigest_c	HASH512_ODIGEST_C
hash512_odigest_d	HASH512_ODIGEST_D
hash512_odigest_e	HASH512_ODIGEST_E
hash512_odigest_f	HASH512_ODIGEST_F
hash512_odigest_g	HASH512_ODIGEST_G
hash512_odigest_h	HASH512_ODIGEST_H
hash512_odigest_i	HASH512_ODIGEST_I
hash512_odigest_j	HASH512_ODIGEST_J
hash512_odigest_k	HASH512_ODIGEST_K
hash512_odigest_l	HASH512_ODIGEST_L
hash512_odigest_m	HASH512_ODIGEST_M
hash512_odigest_n	HASH512_ODIGEST_N
hash512_odigest_o	HASH512_ODIGEST_O
hash512_odigest_p	HASH512_ODIGEST_P
hash512_idigest_a	HASH512_IDIGEST_A
hash512_idigest_b	HASH512_IDIGEST_B
hash512_idigest_c	HASH512_IDIGEST_C
hash512_idigest_d	HASH512_IDIGEST_D
hash512_idigest_e	HASH512_IDIGEST_E
hash512_idigest_f	HASH512_IDIGEST_F
hash512_idigest_g	HASH512_IDIGEST_G
hash512_idigest_h	HASH512_IDIGEST_H
hash512_idigest_i	HASH512_IDIGEST_I
hash512_idigest_j	HASH512_IDIGEST_J
hash512_idigest_k	HASH512_IDIGEST_K
hash512_idigest_l	HASH512_IDIGEST_L
hash512_idigest_m	HASH512_IDIGEST_M
hash512_idigest_n	HASH512_IDIGEST_N
hash512_idigest_o	HASH512_IDIGEST_O
hash512_idigest_p	HASH512_IDIGEST_P
hash512_digest_count	HASH512_DIGEST_COUNT
hash512_mode	HASH512_MODE
hash512_length	HASH512_LENGTH
idigest_a	WRITE: Inner / Initial Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2 / HMAC Key [287:256] for HMAC key proc READ: Intermediate / Inner Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2 / Result Digest/MAC [127:96] for MD5 [159:128] for SHA-1 [223:192] for SHA-2 224 [255:224] for SHA-2 256
idigest_b	WRITE: Inner / Initial Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2 / HMAC Key [319:288] for HMAC key proc READ: Intermediate / Inner Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2 / Result Digest/MAC [95:64] for MD5 [127:96] for SHA-1 [191:160] for SHA-2 224 [223:192] for SHA-2 256
idigest_c	WRITE: Inner / Initial Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA- 2 / HMAC Key [351:320] for HMAC key proc READ: Intermediate / Inner Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA-2 / Result Digest/MAC [63:32] for MD5 [95:64] for SHA-1 [159:128] for SHA-2 224 [191:160] for SHA-2 256
idigest_d	WRITE: Inner / Initial Digest [31:0] for MD5 [63:32] for SHA-1 [159:128] for SHA-2 / HMAC Key [383:352] for HMAC key proc READ: Intermediate / Inner Digest [31:0] for MD5 [63:32] for SHA-1 [159:128] for SHA-2 / Result Digest/MAC [31:0] for MD5 [63:32] for SHA-1 [127:96] for SHA-2 224 [159:128] for SHA-2 256
idigest_e	WRITE: Inner / Initial Digest [31:0] for SHA-1 [127:96] for SHA-2 / HMAC Key [415:384] for HMAC key proc READ: Intermediate / Inner Digest [31:0] for SHA-1 [127:96] for SHA-2 / Result Digest/MAC [31:0] for SHA-1 [95:64] for SHA-2 224 [127:96] for SHA-2 256
idigest_f	WRITE: Inner / Initial Digest [95:64] for SHA-2 / HMAC Key [447:416] for HMAC key proc READ: Intermediate / Inner Digest [95:64] for SHA-2 / Result Digest/MAC [63:32] for SHA-2 224 [95:64] for SHA-2 256
idigest_g	WRITE: Inner / Initial Digest [63:32] for SHA-2 / HMAC Key [479:448] for HMAC key proc READ: Intermediate / Inner Digest [63:32] for SHA-2 / Result Digest/MAC [31:0] for SHA-2 224 [63:32] for SHA-2 256
idigest_h	WRITE: Inner / Initial Digest [31:0] for SHA-2 / HMAC Key [511:480] for HMAC key proc READ: Intermediate / Inner Digest [31:0] for SHA-2 / Result Digest/MAC [31:0] for SHA-2 256
irqenable	Register SHAMD5_IRQENABLE. The SHAMD5_IRQENABLE register contains an enable bit for each unique interrupt for the public side. An interrupt is enabled when both the global enable in SHAMD5_SYSCONFIG (PIT_en) and the bit in this register are both set to 1. An interrupt that is enabled is propagated to the SINTREQUEST_P output. Please note that the dedicated partial hash output (SINTREQUEST_PART_P) is not affected by this register it is only affected by the global enable SHAMD5_SYSCONFIG (PIT_en).
irqstatus	Register SHAMD5_IRQSTATUS
length	WRITE: Block Length / Remaining Byte Count (bytes) READ: Remaining Byte Count. The value programmed MUST be a 64-byte multiple if Close Hash is set to 0. This register is also the trigger to start processing: once this register is written the core will commence requesting input data via DMA or IRQ (if programmed length > 0) and start processing. The remaining byte count for the active operation can be read from this register when the interrupt status register indicates that the operation is suspended due to a context switch request.
mode	Register SHAMD5_MODE
odigest_a	WRITE: Outer Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2 / HMAC Key [31:0] for HMAC key proc READ: Outer Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2
odigest_b	WRITE: Outer Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2 / HMAC Key [63:32] for HMAC key proc READ: Outer Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2
odigest_c	WRITE: Outer Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA-2 / HMAC Key [95:64] for HMAC key proc READ: Outer Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA-2
odigest_d	WRITE: Outer Digest [31:0] for MD5 [63:31] for SHA-1 [159:128] for SHA-2 / HMAC Key [127:96] for HMAC key proc READ: Outer Digest [31:0] for MD5 [63:32] for SHA-1 [159:128] for SHA-2
odigest_e	WRITE: Outer Digest [31:0] for SHA-1 [127:96] for SHA-2 / HMAC Key [159:128] for HMAC key proc READ: Outer Digest [31:0] for SHA-1 [127:96] for SHA-2
odigest_f	WRITE: Outer Digest [95:64] for SHA-2 / HMAC Key [191:160] for HMAC key proc READ: Outer Digest [95:64] for SHA-2
odigest_g	WRITE: Outer Digest [63:32] for SHA-2 / HMAC Key [223:192] for HMAC key proc READ: Outer Digest [63:32] for SHA-2
odigest_h	WRITE: Outer Digest [31:0] for SHA-2 / HMAC Key [255:224] for HMAC key proc READ: Outer Digest [31:0] for SHA-2
revision	Register SHAMD5_REV
sysconfig	Register SHAMD5_SYSCONFIG
sysstatus	Register SHAMD5_SYSSTATUS

Structs

RegisterBlock

Register block

Type Definitions

DATA0_IN	Data input message 0
DATA1_IN	Data input message 1
DATA2_IN	Data input message 2
DATA3_IN	Data input message 3
DATA4_IN	Data input message 4
DATA5_IN	Data input message 5
DATA6_IN	Data input message 6
DATA7_IN	Data input message 7
DATA8_IN	Data input message 8
DATA9_IN	Data input message 9
DATA10_IN	Data input message 10
DATA11_IN	Data input message 11
DATA12_IN	Data input message 12
DATA13_IN	Data input message 13
DATA14_IN	Data input message 14
DATA15_IN	Data input message 15
DIGEST_COUNT	WRITE: Initial Digest Count ([31:6] only [5:0] assumed 0) READ: Result / IntermediateDigest Count The initial digest byte count for hash/HMAC continue operations (HMAC Key Processing = 0 and Use Algorithm Constants = 0) on the Secure World must be written to this register prior to starting the operation by writing to S_HASH_MODE. When either HMAC Key Processing is 1 or Use Algorithm Constants is 1 this register does not need to be written it will be overwritten with 64 (1 hash block of key XOR ipad) or 0 respectively automatically. When starting a HMAC operation from pre-computes (HMAC Key Processing is 0) then the value 64 must be written here to compensate for the appended key XOR ipad block. Note that the value written should always be a 64 byte multiple the lower 6 bits written are ignored. The updated digest byte count (initial digest byte count + bytes processed) can be read from this register when the status register indicates that the operation is done or suspended due to a context switch request or when a Secure World context out DMA is requested. In Advanced DMA mode when not suspended with a partial result reading the SHAMD5_DIGEST_COUNT register triggers the Hash/HMAC Engine to start the next context input DMA. Therefore reading the SHAMD5_DIGEST_COUNT register should always be the last context-read action if not suspended with a partial result (i.e. PartHashReady interrupt not pending).
HASH512_ODIGEST_A	HASH512_ODIGEST_A
HASH512_ODIGEST_B	HASH512_ODIGEST_B
HASH512_ODIGEST_C	HASH512_ODIGEST_C
HASH512_ODIGEST_D	HASH512_ODIGEST_D
HASH512_ODIGEST_E	HASH512_ODIGEST_E
HASH512_ODIGEST_F	HASH512_ODIGEST_F
HASH512_ODIGEST_G	HASH512_ODIGEST_G
HASH512_ODIGEST_H	HASH512_ODIGEST_H
HASH512_ODIGEST_I	HASH512_ODIGEST_I
HASH512_ODIGEST_J	HASH512_ODIGEST_J
HASH512_ODIGEST_K	HASH512_ODIGEST_K
HASH512_ODIGEST_L	HASH512_ODIGEST_L
HASH512_ODIGEST_M	HASH512_ODIGEST_M
HASH512_ODIGEST_N	HASH512_ODIGEST_N
HASH512_ODIGEST_O	HASH512_ODIGEST_O
HASH512_ODIGEST_P	HASH512_ODIGEST_P
HASH512_IDIGEST_A	HASH512_IDIGEST_A
HASH512_IDIGEST_B	HASH512_IDIGEST_B
HASH512_IDIGEST_C	HASH512_IDIGEST_C
HASH512_IDIGEST_D	HASH512_IDIGEST_D
HASH512_IDIGEST_E	HASH512_IDIGEST_E
HASH512_IDIGEST_F	HASH512_IDIGEST_F
HASH512_IDIGEST_G	HASH512_IDIGEST_G
HASH512_IDIGEST_H	HASH512_IDIGEST_H
HASH512_IDIGEST_I	HASH512_IDIGEST_I
HASH512_IDIGEST_J	HASH512_IDIGEST_J
HASH512_IDIGEST_K	HASH512_IDIGEST_K
HASH512_IDIGEST_L	HASH512_IDIGEST_L
HASH512_IDIGEST_M	HASH512_IDIGEST_M
HASH512_IDIGEST_N	HASH512_IDIGEST_N
HASH512_IDIGEST_O	HASH512_IDIGEST_O
HASH512_IDIGEST_P	HASH512_IDIGEST_P
HASH512_DIGEST_COUNT	HASH512_DIGEST_COUNT
HASH512_MODE	HASH512_MODE
HASH512_LENGTH	HASH512_LENGTH
IDIGEST_A	WRITE: Inner / Initial Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2 / HMAC Key [287:256] for HMAC key proc READ: Intermediate / Inner Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2 / Result Digest/MAC [127:96] for MD5 [159:128] for SHA-1 [223:192] for SHA-2 224 [255:224] for SHA-2 256
IDIGEST_B	WRITE: Inner / Initial Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2 / HMAC Key [319:288] for HMAC key proc READ: Intermediate / Inner Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2 / Result Digest/MAC [95:64] for MD5 [127:96] for SHA-1 [191:160] for SHA-2 224 [223:192] for SHA-2 256
IDIGEST_C	WRITE: Inner / Initial Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA- 2 / HMAC Key [351:320] for HMAC key proc READ: Intermediate / Inner Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA-2 / Result Digest/MAC [63:32] for MD5 [95:64] for SHA-1 [159:128] for SHA-2 224 [191:160] for SHA-2 256
IDIGEST_D	WRITE: Inner / Initial Digest [31:0] for MD5 [63:32] for SHA-1 [159:128] for SHA-2 / HMAC Key [383:352] for HMAC key proc READ: Intermediate / Inner Digest [31:0] for MD5 [63:32] for SHA-1 [159:128] for SHA-2 / Result Digest/MAC [31:0] for MD5 [63:32] for SHA-1 [127:96] for SHA-2 224 [159:128] for SHA-2 256
IDIGEST_E	WRITE: Inner / Initial Digest [31:0] for SHA-1 [127:96] for SHA-2 / HMAC Key [415:384] for HMAC key proc READ: Intermediate / Inner Digest [31:0] for SHA-1 [127:96] for SHA-2 / Result Digest/MAC [31:0] for SHA-1 [95:64] for SHA-2 224 [127:96] for SHA-2 256
IDIGEST_F	WRITE: Inner / Initial Digest [95:64] for SHA-2 / HMAC Key [447:416] for HMAC key proc READ: Intermediate / Inner Digest [95:64] for SHA-2 / Result Digest/MAC [63:32] for SHA-2 224 [95:64] for SHA-2 256
IDIGEST_G	WRITE: Inner / Initial Digest [63:32] for SHA-2 / HMAC Key [479:448] for HMAC key proc READ: Intermediate / Inner Digest [63:32] for SHA-2 / Result Digest/MAC [31:0] for SHA-2 224 [63:32] for SHA-2 256
IDIGEST_H	WRITE: Inner / Initial Digest [31:0] for SHA-2 / HMAC Key [511:480] for HMAC key proc READ: Intermediate / Inner Digest [31:0] for SHA-2 / Result Digest/MAC [31:0] for SHA-2 256
IRQENABLE	Register SHAMD5_IRQENABLE. The SHAMD5_IRQENABLE register contains an enable bit for each unique interrupt for the public side. An interrupt is enabled when both the global enable in SHAMD5_SYSCONFIG (PIT_en) and the bit in this register are both set to 1. An interrupt that is enabled is propagated to the SINTREQUEST_P output. Please note that the dedicated partial hash output (SINTREQUEST_PART_P) is not affected by this register it is only affected by the global enable SHAMD5_SYSCONFIG (PIT_en).
IRQSTATUS	Register SHAMD5_IRQSTATUS
LENGTH	WRITE: Block Length / Remaining Byte Count (bytes) READ: Remaining Byte Count. The value programmed MUST be a 64-byte multiple if Close Hash is set to 0. This register is also the trigger to start processing: once this register is written the core will commence requesting input data via DMA or IRQ (if programmed length > 0) and start processing. The remaining byte count for the active operation can be read from this register when the interrupt status register indicates that the operation is suspended due to a context switch request.
MODE	Register SHAMD5_MODE
ODIGEST_A	WRITE: Outer Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2 / HMAC Key [31:0] for HMAC key proc READ: Outer Digest [127:96] for MD5 [159:128] for SHA-1 [255:224] for SHA-2
ODIGEST_B	WRITE: Outer Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2 / HMAC Key [63:32] for HMAC key proc READ: Outer Digest [95:64] for MD5 [127:96] for SHA-1 [223:192] for SHA-2
ODIGEST_C	WRITE: Outer Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA-2 / HMAC Key [95:64] for HMAC key proc READ: Outer Digest [63:32] for MD5 [95:64] for SHA-1 [191:160] for SHA-2
ODIGEST_D	WRITE: Outer Digest [31:0] for MD5 [63:31] for SHA-1 [159:128] for SHA-2 / HMAC Key [127:96] for HMAC key proc READ: Outer Digest [31:0] for MD5 [63:32] for SHA-1 [159:128] for SHA-2
ODIGEST_E	WRITE: Outer Digest [31:0] for SHA-1 [127:96] for SHA-2 / HMAC Key [159:128] for HMAC key proc READ: Outer Digest [31:0] for SHA-1 [127:96] for SHA-2
ODIGEST_F	WRITE: Outer Digest [95:64] for SHA-2 / HMAC Key [191:160] for HMAC key proc READ: Outer Digest [95:64] for SHA-2
ODIGEST_G	WRITE: Outer Digest [63:32] for SHA-2 / HMAC Key [223:192] for HMAC key proc READ: Outer Digest [63:32] for SHA-2
ODIGEST_H	WRITE: Outer Digest [31:0] for SHA-2 / HMAC Key [255:224] for HMAC key proc READ: Outer Digest [31:0] for SHA-2
REVISION	Register SHAMD5_REV
SYSCONFIG	Register SHAMD5_SYSCONFIG
SYSSTATUS	Register SHAMD5_SYSSTATUS