Module cc3220sf::gpioa3::im

0x4000 5410 0x4000 6410 0x4000 7410 0x4002 4410 GPIO Interrupt Mask (GPIOIM)@@ offset 0x410 The GPIOIM register is the interrupt mask register. Setting a bit in the GPIOIM register allows interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the combined interrupt signal. Clearing a bit prevents an interrupt on the corresponding pin from being sent to the interrupt controller. All bits are cleared by a reset.

Type Definitions

R	Reader of register IM
W	Writer for register IM