[−][src]Module cc3220sf::gpioa1
GPIOA1
Modules
| adcctl | This register is not used in cc3xx. ADC trigger via GPIO is not supported. 0x4000 5530 0x4000 6530 0x4000 7530 0x4002 4530 GPIO ADC Control (GPIOADCCTL)@@ offset 0x530 This register is used to configure a GPIO pin as a source for the ADC trigger. Note that if the Port B GPIOADCCTL register is cleared@@ PB4 can still be used as an external trigger for the ADC. This is a legacy mode which allows code written for previous Stellaris devices to operate on this microcontroller. |
| afsel | 0x4000 5420 0x4000 6420 0x4000 7420 0x4002 4420 GPIO Alternate Function Select (GPIOAFSEL)@@ offset 0x420 The GPIOAFSEL register is the mode control select register. If a bit is clear@@ the pin is used as a GPIO and is controlled by the GPIO registers. Setting a bit in this register configures the corresponding GPIO line to be controlled by an associated peripheral. Several possible peripheral functions are multiplexed on each GPIO. The GPIO Port Control (GPIOPCTL) register is used to select one of the possible functions. |
| amsel | 0x4000 5528 0x4000 6528 0x4000 7528 0x4002 4528 The GPIOAMSEL register controls isolation circuits to the analog side of a unified I/O pad. Because the GPIOs may be driven by a 5-V source and affect analog operation@@ analog circuitry requires isolation from the pins when they are not used in their analog function. Each bit of this register controls the isolation circuitry for the corresponding GPIO signal. |
| cr | 0x4000 5524 0x4000 6524 0x4000 7524 0x4002 4524 GPIO Commit (GPIOCR)@@ offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ and GPIODEN registers are committed when a write to these registers is performed. If a bit in the GPIOCR register is cleared@@ the data being written to the corresponding bit in the GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ or GPIODEN registers cannot be committed and retains its previous value. If a bit in the GPIOCR register is set@@ the data being written to the corresponding bit of the GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ or GPIODEN registers is committed to the register and reflects the new value. The contents of the GPIOCR register can only be modified if the status in the GPIOLOCK register is unlocked. Writes to the GPIOCR register are ignored if the status in the GPIOLOCK register is locked. |
| data | 0x4000 5000 0x4000 6000 0x4000 7000 0x4002 4000 GPIO Data (GPIODATA)@@ offset 0x000 The GPIODATA register is the data register. In software control mode@@ values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 653). In order to write to GPIODATA@@ the corresponding bits in the mask@@ resulting from the address bus bits [9:2]@@ must be set. Otherwise@@ the bit values remain unchanged by the write. Similarly@@ the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register@@ bits [9:2]. Bits that are set in the address mask cause the corresponding bits in GPIODATA to be read@@ and bits that are clear in the address mask cause the corresponding bits in GPIODATA to be read as 0@@ regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs@@ or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. |
| den | 0x4000 551C 0x4000 651C 0x4000 751C 0x4002 451C GPIO Digital Enable (GPIODEN)@@ offset 0x51C Note: Pins configured as digital inputs are Schmitt-triggered. The GPIODEN register is the digital enable register. By default@@ all GPIO signals except those listed below are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin as a digital input or output (either GPIO or alternate function)@@ the corresponding GPIODEN bit must be set. |
| dir | 0x4000 5400 0x4000 6400 0x4000 7400 0x4002 4400 GPIO Direction (GPIODIR)@@ offset 0x400 The GPIODIR register is the data direction register. Setting a bit in the GPIODIR register configures the corresponding pin to be an output@@ while clearing a bit configures the corresponding pin to be an input. All bits are cleared by a reset@@ meaning all GPIO pins are inputs by default. |
| dmactl | 0x4000 5534 0x4000 6534 0x4000 7534 0x4002 4534 GPIO DMA Control (GPIODMACTL)@@ offset 0x534 This register is used to configure a GPIO pin as a source for the ?DMA trigger. |
| dr2r | 0x4000 5500 0x4000 6500 0x4000 7500 0x4002 4500 GPIO 2-mA Drive Select (GPIODR2R)@@ offset 0x500 The GPIODR2R register is the 2-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV2 bit for a GPIO signal@@ the corresponding DRV4 bit in the GPIODR4R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. By default@@ all GPIO pins have 2-mA drive. |
| dr4r | 0x4000 5504 0x4000 6504 0x4000 7504 0x4002 4504 GPIO 4-mA Drive Select (GPIODR4R)@@ offset 0x504 The GPIODR4R register is the 4-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV4 bit for a GPIO signal@@ the corresponding DRV2 bit in the GPIODR2R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. |
| dr8r | 0x4000 5508 0x4000 6508 0x4000 7508 0x4002 4508 GPIO 8-mA Drive Select (GPIODR8R)@@ offset 0x508 The GPIODR8R register is the 8-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV8 bit for a GPIO signal@@ the corresponding DRV2 bit in the GPIODR2R register and DRV4 bit in the GPIODR4R register are automatically cleared by hardware. The 8-mA setting is also used for high-current operation. Note: There is no configuration difference between 8-mA and high-current operation. The additional current capacity results from a shift in the VOH/VOL levels. |
| ibe | 0x4000 5408 0x4000 6408 0x4000 7408 0x4002 4408 GPIO Interrupt Both Edges (GPIOIBE)@@ offset 0x408 The GPIOIBE register allows both edges to cause interrupts. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register is set to detect edges@@ setting a bit in the GPIOIBE register configures the corresponding pin to detect both rising and falling edges@@ regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register . Clearing a bit configures the pin to be controlled by the GPIOIEV register. All bits are cleared by a reset. |
| icr | 0x4000 541C 0x4000 641C 0x4000 741C 0x4002 441C GPIO Interrupt Clear (GPIOICR)@@ offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt bit in the GPIORIS and GPIOMIS registers. Writing a 0 has no effect. |
| iev | 0x4000 540C 0x4000 640C 0x4000 740C 0x4002 440C GPIO Interrupt Event (GPIOIEV)@@ offset 0x40C The GPIOIEV register is the interrupt event register. Setting a bit in the GPIOIEV register configures the corresponding pin to detect rising edges or high levels@@ depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register . Clearing a bit configures the pin to detect falling edges or low levels@@ depending on the corresponding bit value in the GPIOIS register. All bits are cleared by a reset. |
| im | 0x4000 5410 0x4000 6410 0x4000 7410 0x4002 4410 GPIO Interrupt Mask (GPIOIM)@@ offset 0x410 The GPIOIM register is the interrupt mask register. Setting a bit in the GPIOIM register allows interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the combined interrupt signal. Clearing a bit prevents an interrupt on the corresponding pin from being sent to the interrupt controller. All bits are cleared by a reset. |
| is | 0x4000 5404 0x4000 6404 0x4000 7404 0x4002 4404 GPIO Interrupt Sense (GPIOIS)@@ offset 0x404 The GPIOIS register is the interrupt sense register. Setting a bit in the GPIOIS register configures the corresponding pin to detect levels@@ while clearing a bit configures the corresponding pin to detect edges. All bits are cleared by a reset. |
| lock | 0x4000 5520 0x4000 6520 0x4000 7520 0x4002 4520 GPIO Lock (GPIOLOCK)@@ offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register . Writing 0x4C4F.434B to the GPIOLOCK register unlocks the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written. Therefore@@ when write accesses are disabled@@ or locked@@ reading the GPIOLOCK register returns 0x0000.0001. When write accesses are enabled@@ or unlocked@@ reading the GPIOLOCK register returns 0x0000.0000. |
| mis | 0x4000 5418 0x4000 6418 0x4000 7418 0x4002 4418 GPIO Masked Interrupt Status (GPIOMIS)@@ offset 0x418 The GPIOMIS register is the masked interrupt status register. If a bit is set in this register@@ the corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear@@ either no interrupt has been generated@@ or the interrupt is masked. If no port pin@@ other than the one that is being used as an ADC trigger@@ is being used to generate interrupts@@ the appropriate Interrupt Set Enable (ENn) register can disable the interrupts for the port@@ and the ADC interrupt can be used to read back the converted data. Otherwise@@ the port interrupt handler must ignore and clear interrupts on the port pin and wait for the ADC interrupt@@ or the ADC interrupt must be disabled in the EN0 register and the port interrupt handler must poll the ADC registers until the conversion is completed. If no port pin@@ other than the one that is being used as an ADC trigger@@ is being used to generate interrupts@@ the appropriate Interrupt Set Enable (ENn) register can disable the interrupts for the port@@ and the ADC interrupt can be used to read back the converted data. Otherwise@@ the port interrupt handler must ignore and clear interrupts on the port pin and wait for the ADC interrupt@@ or the ADC interrupt must be disabled in the EN0 register and the port interrupt handler must poll the ADC registers until the conversion is completed. Note that if the Port B GPIOADCCTL register is cleared@@ PB4 can still be used as an external trigger for the ADC. This is a legacy mode which allows code written for previous Stellaris devices to operate on this microcontroller. GPIOMIS is the state of the interrupt after masking. |
| odr | 0x4000 550C 0x4000 650C 0x4000 750C 0x4002 450C GPIO Open Drain Select (GPIOODR)@@ offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open-drain configuration of the corresponding GPIO pad. When open-drain mode is enabled@@ the corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register . Corresponding bits in the drive strength and slew rate control registers (GPIODR2R@@ GPIODR4R@@ GPIODR8R@@ and GPIOSLR) can be set to achieve the desired rise and fall times. The GPIO acts as an open-drain input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the GPIO is configured as an input@@ the GPIO will remain an input and the open-drain selection has no effect until the GPIO is changed to an output. When using the I2C module@@ in addition to configuring the pin to open drain@@ the GPIO Alternate Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set |
| pcellid0 | 0x4000 5FF0 0x4000 6FF0 0x4000 7FF0 0x4002 4FF0 GPIO PrimeCell Identification 0 (GPIOPCellID0)@@ offset 0xFF0 The GPIOPCellID0@@ GPIOPCellID1@@ GPIOPCellID2@@ and GPIOPCellID3 registers are four 8-bit wide registers@@ that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. |
| pcellid1 | 0x4000 5FF4 0x4000 6FF4 0x4000 7FF4 0x4002 4FF4 GPIO PrimeCell Identification 1 (GPIOPCellID1)@@ offset 0xFF4 The GPIOPCellID0@@ GPIOPCellID1@@ GPIOPCellID2@@ and GPIOPCellID3 registers are four 8-bit wide registers@@ that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. |
| pcellid2 | 0x4000 5FF8 0x4000 6FF8 0x4000 7FF8 0x4002 4FF8 GPIO PrimeCell Identification 2 (GPIOPCellID2)@@ offset 0xFF8 The GPIOPCellID0@@ GPIOPCellID1@@ GPIOPCellID2@@ and GPIOPCellID3 registers are four 8-bit wide registers@@ that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. |
| pcellid3 | 0x4000 5FFC 0x4000 6FFC 0x4000 7FFC 0x4002 4FFC GPIO PrimeCell Identification 3 (GPIOPCellID3)@@ offset 0xFFC The GPIOPCellID0@@ GPIOPCellID1@@ GPIOPCellID2@@ and GPIOPCellID3 registers are four 8-bit wide registers@@ that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system.0xb1 **************************************************************************** |
| pctl | This register is not used in cc3xx. equivalant register exsist outside GPIO IP (refer PAD*_config register in the shared comn space) 0x4000 552C 0x4000 652C 0x4000 752C 0x4002 452C GPIO Port Control (GPIOPCTL)@@ offset 0x52C The GPIOPCTL register is used in conjunction with the GPIOAFSEL register and selects the specific peripheral signal for each GPIO pin when using the alternate function mode. Most bits in the GPIOAFSEL register are cleared on reset@@ therefore most GPIO pins are configured as GPIOs by default. When a bit is set in the GPIOAFSEL register@@ the corresponding GPIO signal is controlled by an associated peripheral. The GPIOPCTL register selects one out of a set of peripheral functions for each GPIO@@ providing additional flexibility in signal definition. |
| pdr | 0x4000 5514 0x4000 6514 0x4000 7514 0x4002 4514 GPIO Pull-Down Select (GPIOPDR)@@ offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set@@ a weak pull-down resistor on the corresponding GPIO signal is enabled. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register |
| periphid0 | 0x4000 5FE0 0x4000 6FE0 0x4000 7FE0 0x4002 4FE0 GPIO Peripheral Identification 0 (GPIOPeriphID0)@@ offset 0xFE0 The GPIOPeriphID0@@ GPIOPeriphID1@@ GPIOPeriphID2@@ and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| periphid1 | 0x4000 5FE4 0x4000 6FE4 0x4000 7FE4 0x4002 4FE4 GPIO Peripheral Identification 1 (GPIOPeriphID1)@@ offset 0xFE4 The GPIOPeriphID0@@ GPIOPeriphID1@@ GPIOPeriphID2@@ and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| periphid2 | 0x4000 5FE8 0x4000 6FE8 0x4000 7FE8 0x4002 4FE8 GPIO Peripheral Identification 2 (GPIOPeriphID2)@@ offset 0xFE8 The GPIOPeriphID0@@ GPIOPeriphID1@@ GPIOPeriphID2@@ and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| periphid3 | 0x4000 5FEC 0x4000 6FEC 0x4000 7FEC 0x4002 4FEC GPIO Peripheral Identification 3 (GPIOPeriphID3)@@ offset 0xFEC The GPIOPeriphID0@@ GPIOPeriphID1@@ GPIOPeriphID2@@ and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| periphid4 | 0x4000 5FD0 0x4000 6FD0 0x4000 7FD0 0x4002 4FD0 GPIO Peripheral Identification 4 (GPIOPeriphID4)@@ offset 0xFD0 The GPIOPeriphID4@@ GPIOPeriphID5@@ GPIOPeriphID6@@ and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| periphid5 | 0x4000 5FD4 0x4000 6FD4 0x4000 7FD4 0x4002 4FD4 GPIO Peripheral Identification 5 (GPIOPeriphID5)@@ offset 0xFD4 The GPIOPeriphID4@@ GPIOPeriphID5@@ GPIOPeriphID6@@ and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| periphid6 | 0x4000 5FD8 0x4000 6FD8 0x4000 7FD8 0x4002 4FD8 GPIO Peripheral Identification 6 (GPIOPeriphID6)@@ offset 0xFD8 The GPIOPeriphID4@@ GPIOPeriphID5@@ GPIOPeriphID6@@ and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| periphid7 | 0x4000 5FDC 0x4000 6FDC 0x4000 7FDC 0x4002 4FDC GPIO Peripheral Identification 7 (GPIOPeriphID7)@@ offset 0xFDC The GPIOPeriphID4@@ GPIOPeriphID5@@ GPIOPeriphID6@@ and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| pur | 0x4000 5510 0x4000 6510 0x4000 7510 0x4002 4510 GPIO Pull-Up Select (GPIOPUR)@@ offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set@@ a weak pull-up resistor on the corresponding GPIO signal is enabled. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register . Write access to this register is protected with the GPIOCR register. Bits in GPIOCR that are cleared prevent writes to the equivalent bit in this register. |
| ris | 0x4000 5414 0x4000 6414 0x4000 7414 0x4002 4414 GPIO Raw Interrupt Status (GPIORIS)@@ offset 0x414 The GPIORIS register is the raw interrupt status register. A bit in this register is set when an interrupt condition occurs on the corresponding GPIO pin. If the corresponding bit in the GPIO Interrupt Mask (GPIOIM) register is set@@ the interrupt is sent to the interrupt controller. Bits read as zero indicate that corresponding input pins have not initiated an interrupt. A bit in this register can be cleared by writing a 1 to the corresponding bit in the GPIO Interrupt Clear (GPIOICR) register. |
| si | 0x4000 5538 0x4000 6538 0x4000 7538 0x4002 4538 GPIO Select Interrupt (GPIOSI)@@ offset 0x538 This register is used to enable individual interrupts for each pin. Note: This register is only available on Port P and Port Q. |
| slr | 0x4000 5518 0x4000 6518 0x4000 7518 0x4002 4518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register |
Structs
| RegisterBlock | Register block |
Type Definitions
| ADCCTL | This register is not used in cc3xx. ADC trigger via GPIO is not supported. 0x4000 5530 0x4000 6530 0x4000 7530 0x4002 4530 GPIO ADC Control (GPIOADCCTL)@@ offset 0x530 This register is used to configure a GPIO pin as a source for the ADC trigger. Note that if the Port B GPIOADCCTL register is cleared@@ PB4 can still be used as an external trigger for the ADC. This is a legacy mode which allows code written for previous Stellaris devices to operate on this microcontroller. |
| AFSEL | 0x4000 5420 0x4000 6420 0x4000 7420 0x4002 4420 GPIO Alternate Function Select (GPIOAFSEL)@@ offset 0x420 The GPIOAFSEL register is the mode control select register. If a bit is clear@@ the pin is used as a GPIO and is controlled by the GPIO registers. Setting a bit in this register configures the corresponding GPIO line to be controlled by an associated peripheral. Several possible peripheral functions are multiplexed on each GPIO. The GPIO Port Control (GPIOPCTL) register is used to select one of the possible functions. |
| AMSEL | 0x4000 5528 0x4000 6528 0x4000 7528 0x4002 4528 The GPIOAMSEL register controls isolation circuits to the analog side of a unified I/O pad. Because the GPIOs may be driven by a 5-V source and affect analog operation@@ analog circuitry requires isolation from the pins when they are not used in their analog function. Each bit of this register controls the isolation circuitry for the corresponding GPIO signal. |
| CR | 0x4000 5524 0x4000 6524 0x4000 7524 0x4002 4524 GPIO Commit (GPIOCR)@@ offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ and GPIODEN registers are committed when a write to these registers is performed. If a bit in the GPIOCR register is cleared@@ the data being written to the corresponding bit in the GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ or GPIODEN registers cannot be committed and retains its previous value. If a bit in the GPIOCR register is set@@ the data being written to the corresponding bit of the GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ or GPIODEN registers is committed to the register and reflects the new value. The contents of the GPIOCR register can only be modified if the status in the GPIOLOCK register is unlocked. Writes to the GPIOCR register are ignored if the status in the GPIOLOCK register is locked. |
| DATA | 0x4000 5000 0x4000 6000 0x4000 7000 0x4002 4000 GPIO Data (GPIODATA)@@ offset 0x000 The GPIODATA register is the data register. In software control mode@@ values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 653). In order to write to GPIODATA@@ the corresponding bits in the mask@@ resulting from the address bus bits [9:2]@@ must be set. Otherwise@@ the bit values remain unchanged by the write. Similarly@@ the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register@@ bits [9:2]. Bits that are set in the address mask cause the corresponding bits in GPIODATA to be read@@ and bits that are clear in the address mask cause the corresponding bits in GPIODATA to be read as 0@@ regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs@@ or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. |
| DEN | 0x4000 551C 0x4000 651C 0x4000 751C 0x4002 451C GPIO Digital Enable (GPIODEN)@@ offset 0x51C Note: Pins configured as digital inputs are Schmitt-triggered. The GPIODEN register is the digital enable register. By default@@ all GPIO signals except those listed below are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin as a digital input or output (either GPIO or alternate function)@@ the corresponding GPIODEN bit must be set. |
| DIR | 0x4000 5400 0x4000 6400 0x4000 7400 0x4002 4400 GPIO Direction (GPIODIR)@@ offset 0x400 The GPIODIR register is the data direction register. Setting a bit in the GPIODIR register configures the corresponding pin to be an output@@ while clearing a bit configures the corresponding pin to be an input. All bits are cleared by a reset@@ meaning all GPIO pins are inputs by default. |
| DMACTL | 0x4000 5534 0x4000 6534 0x4000 7534 0x4002 4534 GPIO DMA Control (GPIODMACTL)@@ offset 0x534 This register is used to configure a GPIO pin as a source for the ?DMA trigger. |
| DR2R | 0x4000 5500 0x4000 6500 0x4000 7500 0x4002 4500 GPIO 2-mA Drive Select (GPIODR2R)@@ offset 0x500 The GPIODR2R register is the 2-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV2 bit for a GPIO signal@@ the corresponding DRV4 bit in the GPIODR4R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. By default@@ all GPIO pins have 2-mA drive. |
| DR4R | 0x4000 5504 0x4000 6504 0x4000 7504 0x4002 4504 GPIO 4-mA Drive Select (GPIODR4R)@@ offset 0x504 The GPIODR4R register is the 4-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV4 bit for a GPIO signal@@ the corresponding DRV2 bit in the GPIODR2R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. |
| DR8R | 0x4000 5508 0x4000 6508 0x4000 7508 0x4002 4508 GPIO 8-mA Drive Select (GPIODR8R)@@ offset 0x508 The GPIODR8R register is the 8-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV8 bit for a GPIO signal@@ the corresponding DRV2 bit in the GPIODR2R register and DRV4 bit in the GPIODR4R register are automatically cleared by hardware. The 8-mA setting is also used for high-current operation. Note: There is no configuration difference between 8-mA and high-current operation. The additional current capacity results from a shift in the VOH/VOL levels. |
| IBE | 0x4000 5408 0x4000 6408 0x4000 7408 0x4002 4408 GPIO Interrupt Both Edges (GPIOIBE)@@ offset 0x408 The GPIOIBE register allows both edges to cause interrupts. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register is set to detect edges@@ setting a bit in the GPIOIBE register configures the corresponding pin to detect both rising and falling edges@@ regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register . Clearing a bit configures the pin to be controlled by the GPIOIEV register. All bits are cleared by a reset. |
| ICR | 0x4000 541C 0x4000 641C 0x4000 741C 0x4002 441C GPIO Interrupt Clear (GPIOICR)@@ offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt bit in the GPIORIS and GPIOMIS registers. Writing a 0 has no effect. |
| IEV | 0x4000 540C 0x4000 640C 0x4000 740C 0x4002 440C GPIO Interrupt Event (GPIOIEV)@@ offset 0x40C The GPIOIEV register is the interrupt event register. Setting a bit in the GPIOIEV register configures the corresponding pin to detect rising edges or high levels@@ depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register . Clearing a bit configures the pin to detect falling edges or low levels@@ depending on the corresponding bit value in the GPIOIS register. All bits are cleared by a reset. |
| IM | 0x4000 5410 0x4000 6410 0x4000 7410 0x4002 4410 GPIO Interrupt Mask (GPIOIM)@@ offset 0x410 The GPIOIM register is the interrupt mask register. Setting a bit in the GPIOIM register allows interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the combined interrupt signal. Clearing a bit prevents an interrupt on the corresponding pin from being sent to the interrupt controller. All bits are cleared by a reset. |
| IS | 0x4000 5404 0x4000 6404 0x4000 7404 0x4002 4404 GPIO Interrupt Sense (GPIOIS)@@ offset 0x404 The GPIOIS register is the interrupt sense register. Setting a bit in the GPIOIS register configures the corresponding pin to detect levels@@ while clearing a bit configures the corresponding pin to detect edges. All bits are cleared by a reset. |
| LOCK | 0x4000 5520 0x4000 6520 0x4000 7520 0x4002 4520 GPIO Lock (GPIOLOCK)@@ offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register . Writing 0x4C4F.434B to the GPIOLOCK register unlocks the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written. Therefore@@ when write accesses are disabled@@ or locked@@ reading the GPIOLOCK register returns 0x0000.0001. When write accesses are enabled@@ or unlocked@@ reading the GPIOLOCK register returns 0x0000.0000. |
| MIS | 0x4000 5418 0x4000 6418 0x4000 7418 0x4002 4418 GPIO Masked Interrupt Status (GPIOMIS)@@ offset 0x418 The GPIOMIS register is the masked interrupt status register. If a bit is set in this register@@ the corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear@@ either no interrupt has been generated@@ or the interrupt is masked. If no port pin@@ other than the one that is being used as an ADC trigger@@ is being used to generate interrupts@@ the appropriate Interrupt Set Enable (ENn) register can disable the interrupts for the port@@ and the ADC interrupt can be used to read back the converted data. Otherwise@@ the port interrupt handler must ignore and clear interrupts on the port pin and wait for the ADC interrupt@@ or the ADC interrupt must be disabled in the EN0 register and the port interrupt handler must poll the ADC registers until the conversion is completed. If no port pin@@ other than the one that is being used as an ADC trigger@@ is being used to generate interrupts@@ the appropriate Interrupt Set Enable (ENn) register can disable the interrupts for the port@@ and the ADC interrupt can be used to read back the converted data. Otherwise@@ the port interrupt handler must ignore and clear interrupts on the port pin and wait for the ADC interrupt@@ or the ADC interrupt must be disabled in the EN0 register and the port interrupt handler must poll the ADC registers until the conversion is completed. Note that if the Port B GPIOADCCTL register is cleared@@ PB4 can still be used as an external trigger for the ADC. This is a legacy mode which allows code written for previous Stellaris devices to operate on this microcontroller. GPIOMIS is the state of the interrupt after masking. |
| ODR | 0x4000 550C 0x4000 650C 0x4000 750C 0x4002 450C GPIO Open Drain Select (GPIOODR)@@ offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open-drain configuration of the corresponding GPIO pad. When open-drain mode is enabled@@ the corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register . Corresponding bits in the drive strength and slew rate control registers (GPIODR2R@@ GPIODR4R@@ GPIODR8R@@ and GPIOSLR) can be set to achieve the desired rise and fall times. The GPIO acts as an open-drain input if the corresponding bit in the GPIODIR register is cleared. If open drain is selected while the GPIO is configured as an input@@ the GPIO will remain an input and the open-drain selection has no effect until the GPIO is changed to an output. When using the I2C module@@ in addition to configuring the pin to open drain@@ the GPIO Alternate Function Select (GPIOAFSEL) register bits for the I2C clock and data pins should be set |
| PCELLID0 | 0x4000 5FF0 0x4000 6FF0 0x4000 7FF0 0x4002 4FF0 GPIO PrimeCell Identification 0 (GPIOPCellID0)@@ offset 0xFF0 The GPIOPCellID0@@ GPIOPCellID1@@ GPIOPCellID2@@ and GPIOPCellID3 registers are four 8-bit wide registers@@ that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. |
| PCELLID1 | 0x4000 5FF4 0x4000 6FF4 0x4000 7FF4 0x4002 4FF4 GPIO PrimeCell Identification 1 (GPIOPCellID1)@@ offset 0xFF4 The GPIOPCellID0@@ GPIOPCellID1@@ GPIOPCellID2@@ and GPIOPCellID3 registers are four 8-bit wide registers@@ that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. |
| PCELLID2 | 0x4000 5FF8 0x4000 6FF8 0x4000 7FF8 0x4002 4FF8 GPIO PrimeCell Identification 2 (GPIOPCellID2)@@ offset 0xFF8 The GPIOPCellID0@@ GPIOPCellID1@@ GPIOPCellID2@@ and GPIOPCellID3 registers are four 8-bit wide registers@@ that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. |
| PCELLID3 | 0x4000 5FFC 0x4000 6FFC 0x4000 7FFC 0x4002 4FFC GPIO PrimeCell Identification 3 (GPIOPCellID3)@@ offset 0xFFC The GPIOPCellID0@@ GPIOPCellID1@@ GPIOPCellID2@@ and GPIOPCellID3 registers are four 8-bit wide registers@@ that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system.0xb1 **************************************************************************** |
| PCTL | This register is not used in cc3xx. equivalant register exsist outside GPIO IP (refer PAD*_config register in the shared comn space) 0x4000 552C 0x4000 652C 0x4000 752C 0x4002 452C GPIO Port Control (GPIOPCTL)@@ offset 0x52C The GPIOPCTL register is used in conjunction with the GPIOAFSEL register and selects the specific peripheral signal for each GPIO pin when using the alternate function mode. Most bits in the GPIOAFSEL register are cleared on reset@@ therefore most GPIO pins are configured as GPIOs by default. When a bit is set in the GPIOAFSEL register@@ the corresponding GPIO signal is controlled by an associated peripheral. The GPIOPCTL register selects one out of a set of peripheral functions for each GPIO@@ providing additional flexibility in signal definition. |
| PDR | 0x4000 5514 0x4000 6514 0x4000 7514 0x4002 4514 GPIO Pull-Down Select (GPIOPDR)@@ offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set@@ a weak pull-down resistor on the corresponding GPIO signal is enabled. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register |
| PERIPHID0 | 0x4000 5FE0 0x4000 6FE0 0x4000 7FE0 0x4002 4FE0 GPIO Peripheral Identification 0 (GPIOPeriphID0)@@ offset 0xFE0 The GPIOPeriphID0@@ GPIOPeriphID1@@ GPIOPeriphID2@@ and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| PERIPHID1 | 0x4000 5FE4 0x4000 6FE4 0x4000 7FE4 0x4002 4FE4 GPIO Peripheral Identification 1 (GPIOPeriphID1)@@ offset 0xFE4 The GPIOPeriphID0@@ GPIOPeriphID1@@ GPIOPeriphID2@@ and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| PERIPHID2 | 0x4000 5FE8 0x4000 6FE8 0x4000 7FE8 0x4002 4FE8 GPIO Peripheral Identification 2 (GPIOPeriphID2)@@ offset 0xFE8 The GPIOPeriphID0@@ GPIOPeriphID1@@ GPIOPeriphID2@@ and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| PERIPHID3 | 0x4000 5FEC 0x4000 6FEC 0x4000 7FEC 0x4002 4FEC GPIO Peripheral Identification 3 (GPIOPeriphID3)@@ offset 0xFEC The GPIOPeriphID0@@ GPIOPeriphID1@@ GPIOPeriphID2@@ and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| PERIPHID4 | 0x4000 5FD0 0x4000 6FD0 0x4000 7FD0 0x4002 4FD0 GPIO Peripheral Identification 4 (GPIOPeriphID4)@@ offset 0xFD0 The GPIOPeriphID4@@ GPIOPeriphID5@@ GPIOPeriphID6@@ and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| PERIPHID5 | 0x4000 5FD4 0x4000 6FD4 0x4000 7FD4 0x4002 4FD4 GPIO Peripheral Identification 5 (GPIOPeriphID5)@@ offset 0xFD4 The GPIOPeriphID4@@ GPIOPeriphID5@@ GPIOPeriphID6@@ and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| PERIPHID6 | 0x4000 5FD8 0x4000 6FD8 0x4000 7FD8 0x4002 4FD8 GPIO Peripheral Identification 6 (GPIOPeriphID6)@@ offset 0xFD8 The GPIOPeriphID4@@ GPIOPeriphID5@@ GPIOPeriphID6@@ and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| PERIPHID7 | 0x4000 5FDC 0x4000 6FDC 0x4000 7FDC 0x4002 4FDC GPIO Peripheral Identification 7 (GPIOPeriphID7)@@ offset 0xFDC The GPIOPeriphID4@@ GPIOPeriphID5@@ GPIOPeriphID6@@ and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register@@ used by software to identify the peripheral. |
| PUR | 0x4000 5510 0x4000 6510 0x4000 7510 0x4002 4510 GPIO Pull-Up Select (GPIOPUR)@@ offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set@@ a weak pull-up resistor on the corresponding GPIO signal is enabled. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register . Write access to this register is protected with the GPIOCR register. Bits in GPIOCR that are cleared prevent writes to the equivalent bit in this register. |
| RIS | 0x4000 5414 0x4000 6414 0x4000 7414 0x4002 4414 GPIO Raw Interrupt Status (GPIORIS)@@ offset 0x414 The GPIORIS register is the raw interrupt status register. A bit in this register is set when an interrupt condition occurs on the corresponding GPIO pin. If the corresponding bit in the GPIO Interrupt Mask (GPIOIM) register is set@@ the interrupt is sent to the interrupt controller. Bits read as zero indicate that corresponding input pins have not initiated an interrupt. A bit in this register can be cleared by writing a 1 to the corresponding bit in the GPIO Interrupt Clear (GPIOICR) register. |
| SI | 0x4000 5538 0x4000 6538 0x4000 7538 0x4002 4538 GPIO Select Interrupt (GPIOSI)@@ offset 0x538 This register is used to enable individual interrupts for each pin. Note: This register is only available on Port P and Port Q. |
| SLR | 0x4000 5518 0x4000 6518 0x4000 7518 0x4002 4518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register |