Module cc3220sf::gpioa0::dr2r

0x4000 5500 0x4000 6500 0x4000 7500 0x4002 4500 GPIO 2-mA Drive Select (GPIODR2R)@@ offset 0x500 The GPIODR2R register is the 2-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV2 bit for a GPIO signal@@ the corresponding DRV4 bit in the GPIODR4R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. By default@@ all GPIO pins have 2-mA drive.

Type Definitions

R	Reader of register DR2R
W	Writer for register DR2R