[−][src]Module cc3220sf::des
DES
Modules
| ctrl | CTRL |
| data_h | Data register(MSW) to read/write encrypted/decrypted data. |
| data_l | Data register(LSW) to read/write encrypted/decrypted data. |
| irqenable | This register contains an enable bit for each unique interrupt generated by the module. It matches the layout of DES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to 1 **************************************************************************** |
| irqstatus | This register indicates the interrupt status. If one of the interrupt bits is set the interrupt output will be asserted |
| iv_h | Initialization vector MSW |
| iv_l | Initialization vector LSW |
| key1_l | KEY1 (LSW) for 128-bit key/192-bit key |
| key1_h | KEY1 (LSW) for 128-bit key/192-bit key |
| key2_l | KEY2 (LSW) for 192-bit key |
| key2_h | KEY2 (MSW) for 192-bit key |
| key3_l | KEY3 (LSW) for 192-bit key |
| key3_h | KEY3 (MSW) for 192-bit key |
| length | Indicates the cryptographic data length in bytes for all modes. Once processing is started with this context this length decrements to zero. Data lengths up to (2^32 1) bytes are allowed. A write to this register triggers the engine to start using this context. For a Host read operation these registers return all-zeroes. |
| revision | REVISION |
| sysconfig | SYSCONFIG |
| sysstatus | SYSSTATUS |
Structs
| RegisterBlock | Register block |
Type Definitions
| CTRL | CTRL |
| DATA_H | Data register(MSW) to read/write encrypted/decrypted data. |
| DATA_L | Data register(LSW) to read/write encrypted/decrypted data. |
| IRQENABLE | This register contains an enable bit for each unique interrupt generated by the module. It matches the layout of DES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to 1 **************************************************************************** |
| IRQSTATUS | This register indicates the interrupt status. If one of the interrupt bits is set the interrupt output will be asserted |
| IV_H | Initialization vector MSW |
| IV_L | Initialization vector LSW |
| KEY1_L | KEY1 (LSW) for 128-bit key/192-bit key |
| KEY1_H | KEY1 (LSW) for 128-bit key/192-bit key |
| KEY2_L | KEY2 (LSW) for 192-bit key |
| KEY2_H | KEY2 (MSW) for 192-bit key |
| KEY3_L | KEY3 (LSW) for 192-bit key |
| KEY3_H | KEY3 (MSW) for 192-bit key |
| LENGTH | Indicates the cryptographic data length in bytes for all modes. Once processing is started with this context this length decrements to zero. Data lengths up to (2^32 1) bytes are allowed. A write to this register triggers the engine to start using this context. For a Host read operation these registers return all-zeroes. |
| REVISION | REVISION |
| SYSCONFIG | SYSCONFIG |
| SYSSTATUS | SYSSTATUS |