[−][src]Module cc3220sf::camera
CAMERA
Modules
| cc_ctrl | This register controls the various parameters of the Camera Core block (CCP & Parallel Mode) |
| cc_ctrl_dma | This register controls the DMA interface of the Camera Core block (CCP & Parallel Mode) |
| cc_ctrl_xclk | This register control the value of the clock divisor used to generate the external clock (Parallel Mode) |
| cc_fifo_data | This register allows to write to the FIFO and read from the FIFO (CCP & Parallel Mode) |
| cc_gen_par | This register shows the values of the generic parameters of the module **************************************************************************** |
| cc_irqenable | The interrupt enable register allows to enable/disable the module internal sources of interrupt on an event-by-event basis (CCP & Parallel Mode) |
| cc_irqstatus | The interrupt status regroups all the status of the module internal events that can generate an interrupt (CCP & Parallel Mode) |
| cc_revision | This register contains the IP revision code ( Parallel Mode) |
| cc_sysconfig | This register controls the various parameters of the OCP interface (CCP and Parallel Mode) |
| cc_sysstatus | This register provides status information about the module excluding the interrupt status information (CCP and Parallel Mode) |
| cc_test | This register shows the status of some important variables of the camera core module (CCP & Parallel Mode) |
Structs
| RegisterBlock | Register block |
Type Definitions
| CC_CTRL | This register controls the various parameters of the Camera Core block (CCP & Parallel Mode) |
| CC_CTRL_DMA | This register controls the DMA interface of the Camera Core block (CCP & Parallel Mode) |
| CC_CTRL_XCLK | This register control the value of the clock divisor used to generate the external clock (Parallel Mode) |
| CC_FIFO_DATA | This register allows to write to the FIFO and read from the FIFO (CCP & Parallel Mode) |
| CC_GEN_PAR | This register shows the values of the generic parameters of the module **************************************************************************** |
| CC_IRQENABLE | The interrupt enable register allows to enable/disable the module internal sources of interrupt on an event-by-event basis (CCP & Parallel Mode) |
| CC_IRQSTATUS | The interrupt status regroups all the status of the module internal events that can generate an interrupt (CCP & Parallel Mode) |
| CC_REVISION | This register contains the IP revision code ( Parallel Mode) |
| CC_SYSCONFIG | This register controls the various parameters of the OCP interface (CCP and Parallel Mode) |
| CC_SYSSTATUS | This register provides status information about the module excluding the interrupt status information (CCP and Parallel Mode) |
| CC_TEST | This register shows the status of some important variables of the camera core module (CCP & Parallel Mode) |