[−][src]Module cc3220sf::adc
ADC
Modules
| ch0_gain | Channel 0 gain setting |
| ch0_irq_en | Channel 0 interrupt enable register |
| ch0_fifo_lvl | channel 0 FIFO Level register |
| ch0_irq_status | Channel 0 interrupt status register |
| ch1_gain | Channel 1 gain setting |
| ch1_irq_en | Channel 1 interrupt enable register |
| ch1_irq_status | Channel 1 interrupt status register |
| ch1_fifo_lvl | Channel 1 interrupt status register |
| ch2_gain | Channel 2 gain setting |
| ch2_irq_en | Channel 2 interrupt enable register |
| ch2_irq_status | CH2_IRQ_STATUS |
| ch2_fifo_lvl | CH2_FIFO_LVL |
| ch3_gain | Channel 3 gain setting |
| ch3_irq_en | Channel 3 interrupt enable register |
| ch3_irq_status | Channel 3 interrupt status register |
| ch3_fifo_lvl | Channel 3 interrupt status register |
| ch4_gain | Channel 4 gain setting |
| ch4_irq_en | Channel 4 interrupt enable register |
| ch4_irq_status | Channel 4 interrupt status register |
| ch4_fifo_lvl | Channel 4 interrupt status register |
| ch5_gain | Channel 5 gain setting |
| ch5_irq_en | Channel 5 interrupt enable register |
| ch5_irq_status | CH5_IRQ_STATUS |
| ch5_fifo_lvl | CH5_FIFO_LVL |
| ch6_gain | Channel 6 gain setting |
| ch6_irq_en | Channel 6 interrupt enable register |
| ch6_irq_status | Channel 6 interrupt status register |
| ch6_fifo_lvl | Channel 6 interrupt status register |
| ch7_gain | Channel 7 gain setting |
| ch7_irq_en | Channel 7 interrupt enable register |
| ch7_irq_status | Channel 7 interrupt status register |
| ch7_fifo_lvl | Channel 7 interrupt status register |
| ch_enable | CH_ENABLE |
| channel0fifodata | CH0 FIFO DATA register |
| channel1fifodata | CH1 FIFO DATA register |
| channel2fifodata | CH2 FIFO DATA register |
| channel3fifodata | CH3 FIFO DATA register |
| channel4fifodata | CH4 FIFO DATA register |
| channel5fifodata | CH5 FIFO DATA register |
| channel6fifodata | CH6 FIFO DATA register |
| channel7fifodata | CH7 FIFO DATA register |
| ctrl | ADC control register. |
| dma_mode_en | DMA mode enable register |
| timer_configuration | ADC timer configuration register |
| timer_current_count | ADC timer current count register |
Structs
| RegisterBlock | Register block |
Type Definitions
| CH0_GAIN | Channel 0 gain setting |
| CH0_IRQ_EN | Channel 0 interrupt enable register |
| CH0_FIFO_LVL | channel 0 FIFO Level register |
| CH0_IRQ_STATUS | Channel 0 interrupt status register |
| CH1_GAIN | Channel 1 gain setting |
| CH1_IRQ_EN | Channel 1 interrupt enable register |
| CH1_IRQ_STATUS | Channel 1 interrupt status register |
| CH1_FIFO_LVL | Channel 1 interrupt status register |
| CH2_GAIN | Channel 2 gain setting |
| CH2_IRQ_EN | Channel 2 interrupt enable register |
| CH2_IRQ_STATUS | CH2_IRQ_STATUS |
| CH2_FIFO_LVL | CH2_FIFO_LVL |
| CH3_GAIN | Channel 3 gain setting |
| CH3_IRQ_EN | Channel 3 interrupt enable register |
| CH3_IRQ_STATUS | Channel 3 interrupt status register |
| CH3_FIFO_LVL | Channel 3 interrupt status register |
| CH4_GAIN | Channel 4 gain setting |
| CH4_IRQ_EN | Channel 4 interrupt enable register |
| CH4_IRQ_STATUS | Channel 4 interrupt status register |
| CH4_FIFO_LVL | Channel 4 interrupt status register |
| CH5_GAIN | Channel 5 gain setting |
| CH5_IRQ_EN | Channel 5 interrupt enable register |
| CH5_IRQ_STATUS | CH5_IRQ_STATUS |
| CH5_FIFO_LVL | CH5_FIFO_LVL |
| CH6_GAIN | Channel 6 gain setting |
| CH6_IRQ_EN | Channel 6 interrupt enable register |
| CH6_IRQ_STATUS | Channel 6 interrupt status register |
| CH6_FIFO_LVL | Channel 6 interrupt status register |
| CH7_GAIN | Channel 7 gain setting |
| CH7_IRQ_EN | Channel 7 interrupt enable register |
| CH7_IRQ_STATUS | Channel 7 interrupt status register |
| CH7_FIFO_LVL | Channel 7 interrupt status register |
| CHANNEL0FIFODATA | CH0 FIFO DATA register |
| CHANNEL1FIFODATA | CH1 FIFO DATA register |
| CHANNEL2FIFODATA | CH2 FIFO DATA register |
| CHANNEL3FIFODATA | CH3 FIFO DATA register |
| CHANNEL4FIFODATA | CH4 FIFO DATA register |
| CHANNEL5FIFODATA | CH5 FIFO DATA register |
| CHANNEL6FIFODATA | CH6 FIFO DATA register |
| CHANNEL7FIFODATA | CH7 FIFO DATA register |
| CH_ENABLE | CH_ENABLE |
| CTRL | ADC control register. |
| DMA_MODE_EN | DMA mode enable register |
| TIMER_CONFIGURATION | ADC timer configuration register |
| TIMER_CURRENT_COUNT | ADC timer current count register |