Module cc2650::event

Event Fabric Component Definition

Modules

auxsel0	Output Selection for AUX Subscriber 0
cm3nmisel0	Output Selection for NMI Subscriber 0
cpuirqsel0	Output Selection for CPU Interrupt 0
cpuirqsel1	Output Selection for CPU Interrupt 1
cpuirqsel2	Output Selection for CPU Interrupt 2
cpuirqsel3	Output Selection for CPU Interrupt 3
cpuirqsel4	Output Selection for CPU Interrupt 4
cpuirqsel5	Output Selection for CPU Interrupt 5
cpuirqsel6	Output Selection for CPU Interrupt 6
cpuirqsel7	Output Selection for CPU Interrupt 7
cpuirqsel8	Output Selection for CPU Interrupt 8
cpuirqsel9	Output Selection for CPU Interrupt 9
cpuirqsel10	Output Selection for CPU Interrupt 10
cpuirqsel11	Output Selection for CPU Interrupt 11
cpuirqsel12	Output Selection for CPU Interrupt 12
cpuirqsel13	Output Selection for CPU Interrupt 13
cpuirqsel14	Output Selection for CPU Interrupt 14
cpuirqsel15	Output Selection for CPU Interrupt 15
cpuirqsel16	Output Selection for CPU Interrupt 16
cpuirqsel17	Output Selection for CPU Interrupt 17
cpuirqsel18	Output Selection for CPU Interrupt 18
cpuirqsel19	Output Selection for CPU Interrupt 19
cpuirqsel20	Output Selection for CPU Interrupt 20
cpuirqsel21	Output Selection for CPU Interrupt 21
cpuirqsel22	Output Selection for CPU Interrupt 22
cpuirqsel23	Output Selection for CPU Interrupt 23
cpuirqsel24	Output Selection for CPU Interrupt 24
cpuirqsel25	Output Selection for CPU Interrupt 25
cpuirqsel26	Output Selection for CPU Interrupt 26
cpuirqsel27	Output Selection for CPU Interrupt 27
cpuirqsel28	Output Selection for CPU Interrupt 28
cpuirqsel29	Output Selection for CPU Interrupt 29
cpuirqsel30	Output Selection for CPU Interrupt 30
cpuirqsel31	Output Selection for CPU Interrupt 31
cpuirqsel32	Output Selection for CPU Interrupt 32
cpuirqsel33	Output Selection for CPU Interrupt 33
frzsel0	Output Selection for FRZ Subscriber The halted debug signal is passed to peripherals such as the General Purpose Timer, Sensor Controller with Digital and Analog Peripherals (AUX), Radio, and RTC. When the system CPU halts, the connected peripherals that have freeze enabled also halt. The programmable output can be set to static values of 0 or 1, and can also be set to pass the halted signal.
gpt0acaptsel	Output Selection for GPT0 0
gpt0bcaptsel	Output Selection for GPT0 1
gpt1acaptsel	Output Selection for GPT1 0
gpt1bcaptsel	Output Selection for GPT1 1
gpt2acaptsel	Output Selection for GPT2 0
gpt2bcaptsel	Output Selection for GPT2 1
gpt3acaptsel	Output Selection for GPT3 0
gpt3bcaptsel	Output Selection for GPT3 1
i2sstmpsel0	Output Selection for I2S Subscriber 0
rfcsel0	Output Selection for RFC Event 0
rfcsel1	Output Selection for RFC Event 1
rfcsel2	Output Selection for RFC Event 2
rfcsel3	Output Selection for RFC Event 3
rfcsel4	Output Selection for RFC Event 4
rfcsel5	Output Selection for RFC Event 5
rfcsel6	Output Selection for RFC Event 6
rfcsel7	Output Selection for RFC Event 7
rfcsel8	Output Selection for RFC Event 8
rfcsel9	Output Selection for RFC Event 9
swev	Set or Clear Software Events
udmach0ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach0bsel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach1ssel	Output Selection for DMA Channel 1 SREQ
udmach1bsel	Output Selection for DMA Channel 1 REQ
udmach2ssel	Output Selection for DMA Channel 2 SREQ
udmach2bsel	Output Selection for DMA Channel 2 REQ
udmach3ssel	Output Selection for DMA Channel 3 SREQ
udmach3bsel	Output Selection for DMA Channel 3 REQ
udmach4ssel	Output Selection for DMA Channel 4 SREQ
udmach4bsel	Output Selection for DMA Channel 4 REQ
udmach5ssel	Output Selection for DMA Channel 5 SREQ
udmach5bsel	Output Selection for DMA Channel 5 REQ
udmach6ssel	Output Selection for DMA Channel 6 SREQ
udmach6bsel	Output Selection for DMA Channel 6 REQ
udmach7ssel	Output Selection for DMA Channel 7 SREQ
udmach7bsel	Output Selection for DMA Channel 7 REQ
udmach8ssel	Output Selection for DMA Channel 8 SREQ Single request is ignored for this channel
udmach8bsel	Output Selection for DMA Channel 8 REQ
udmach9ssel	Output Selection for DMA Channel 9 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS
udmach9bsel	Output Selection for DMA Channel 9 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS
udmach10ssel	Output Selection for DMA Channel 10 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS
udmach10bsel	Output Selection for DMA Channel 10 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS
udmach11ssel	Output Selection for DMA Channel 11 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS
udmach11bsel	Output Selection for DMA Channel 11 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS
udmach12ssel	Output Selection for DMA Channel 12 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS
udmach12bsel	Output Selection for DMA Channel 12 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS
udmach13ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach13bsel	Output Selection for DMA Channel 13 REQ
udmach14ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach14bsel	Output Selection for DMA Channel 14 REQ
udmach15ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach15bsel	Output Selection for DMA Channel 15 REQ
udmach16ssel	Output Selection for DMA Channel 16 SREQ
udmach16bsel	Output Selection for DMA Channel 16 REQ
udmach17ssel	Output Selection for DMA Channel 17 SREQ
udmach17bsel	Output Selection for DMA Channel 17 REQ
udmach18ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach18bsel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach19ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach19bsel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach20ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach20bsel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach21ssel	Output Selection for DMA Channel 21 SREQ
udmach21bsel	Output Selection for DMA Channel 21 REQ
udmach22ssel	Output Selection for DMA Channel 22 SREQ
udmach22bsel	Output Selection for DMA Channel 22 REQ
udmach23ssel	Output Selection for DMA Channel 23 SREQ
udmach23bsel	Output Selection for DMA Channel 23 REQ
udmach24ssel	Output Selection for DMA Channel 24 SREQ
udmach24bsel	Output Selection for DMA Channel 24 REQ
udmach25ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach25bsel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach26ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach26bsel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach27ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach27bsel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach28ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach28bsel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach29ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach29bsel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach30ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach30bsel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach31ssel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
udmach31bsel	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

Structs

AUXSEL0	Output Selection for AUX Subscriber 0
CM3NMISEL0	Output Selection for NMI Subscriber 0
CPUIRQSEL0	Output Selection for CPU Interrupt 0
CPUIRQSEL1	Output Selection for CPU Interrupt 1
CPUIRQSEL2	Output Selection for CPU Interrupt 2
CPUIRQSEL3	Output Selection for CPU Interrupt 3
CPUIRQSEL4	Output Selection for CPU Interrupt 4
CPUIRQSEL5	Output Selection for CPU Interrupt 5
CPUIRQSEL6	Output Selection for CPU Interrupt 6
CPUIRQSEL7	Output Selection for CPU Interrupt 7
CPUIRQSEL8	Output Selection for CPU Interrupt 8
CPUIRQSEL9	Output Selection for CPU Interrupt 9
CPUIRQSEL10	Output Selection for CPU Interrupt 10
CPUIRQSEL11	Output Selection for CPU Interrupt 11
CPUIRQSEL12	Output Selection for CPU Interrupt 12
CPUIRQSEL13	Output Selection for CPU Interrupt 13
CPUIRQSEL14	Output Selection for CPU Interrupt 14
CPUIRQSEL15	Output Selection for CPU Interrupt 15
CPUIRQSEL16	Output Selection for CPU Interrupt 16
CPUIRQSEL17	Output Selection for CPU Interrupt 17
CPUIRQSEL18	Output Selection for CPU Interrupt 18
CPUIRQSEL19	Output Selection for CPU Interrupt 19
CPUIRQSEL20	Output Selection for CPU Interrupt 20
CPUIRQSEL21	Output Selection for CPU Interrupt 21
CPUIRQSEL22	Output Selection for CPU Interrupt 22
CPUIRQSEL23	Output Selection for CPU Interrupt 23
CPUIRQSEL24	Output Selection for CPU Interrupt 24
CPUIRQSEL25	Output Selection for CPU Interrupt 25
CPUIRQSEL26	Output Selection for CPU Interrupt 26
CPUIRQSEL27	Output Selection for CPU Interrupt 27
CPUIRQSEL28	Output Selection for CPU Interrupt 28
CPUIRQSEL29	Output Selection for CPU Interrupt 29
CPUIRQSEL30	Output Selection for CPU Interrupt 30
CPUIRQSEL31	Output Selection for CPU Interrupt 31
CPUIRQSEL32	Output Selection for CPU Interrupt 32
CPUIRQSEL33	Output Selection for CPU Interrupt 33
FRZSEL0	Output Selection for FRZ Subscriber The halted debug signal is passed to peripherals such as the General Purpose Timer, Sensor Controller with Digital and Analog Peripherals (AUX), Radio, and RTC. When the system CPU halts, the connected peripherals that have freeze enabled also halt. The programmable output can be set to static values of 0 or 1, and can also be set to pass the halted signal.
GPT0ACAPTSEL	Output Selection for GPT0 0
GPT0BCAPTSEL	Output Selection for GPT0 1
GPT1ACAPTSEL	Output Selection for GPT1 0
GPT1BCAPTSEL	Output Selection for GPT1 1
GPT2ACAPTSEL	Output Selection for GPT2 0
GPT2BCAPTSEL	Output Selection for GPT2 1
GPT3ACAPTSEL	Output Selection for GPT3 0
GPT3BCAPTSEL	Output Selection for GPT3 1
I2SSTMPSEL0	Output Selection for I2S Subscriber 0
RFCSEL0	Output Selection for RFC Event 0
RFCSEL1	Output Selection for RFC Event 1
RFCSEL2	Output Selection for RFC Event 2
RFCSEL3	Output Selection for RFC Event 3
RFCSEL4	Output Selection for RFC Event 4
RFCSEL5	Output Selection for RFC Event 5
RFCSEL6	Output Selection for RFC Event 6
RFCSEL7	Output Selection for RFC Event 7
RFCSEL8	Output Selection for RFC Event 8
RFCSEL9	Output Selection for RFC Event 9
RegisterBlock	Register block
SWEV	Set or Clear Software Events
UDMACH0SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH0BSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH1SSEL	Output Selection for DMA Channel 1 SREQ
UDMACH1BSEL	Output Selection for DMA Channel 1 REQ
UDMACH2SSEL	Output Selection for DMA Channel 2 SREQ
UDMACH2BSEL	Output Selection for DMA Channel 2 REQ
UDMACH3SSEL	Output Selection for DMA Channel 3 SREQ
UDMACH3BSEL	Output Selection for DMA Channel 3 REQ
UDMACH4SSEL	Output Selection for DMA Channel 4 SREQ
UDMACH4BSEL	Output Selection for DMA Channel 4 REQ
UDMACH5SSEL	Output Selection for DMA Channel 5 SREQ
UDMACH5BSEL	Output Selection for DMA Channel 5 REQ
UDMACH6SSEL	Output Selection for DMA Channel 6 SREQ
UDMACH6BSEL	Output Selection for DMA Channel 6 REQ
UDMACH7SSEL	Output Selection for DMA Channel 7 SREQ
UDMACH7BSEL	Output Selection for DMA Channel 7 REQ
UDMACH8SSEL	Output Selection for DMA Channel 8 SREQ Single request is ignored for this channel
UDMACH8BSEL	Output Selection for DMA Channel 8 REQ
UDMACH9SSEL	Output Selection for DMA Channel 9 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS
UDMACH9BSEL	Output Selection for DMA Channel 9 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS
UDMACH10SSEL	Output Selection for DMA Channel 10 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS
UDMACH10BSEL	Output Selection for DMA Channel 10 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS
UDMACH11SSEL	Output Selection for DMA Channel 11 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS
UDMACH11BSEL	Output Selection for DMA Channel 11 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS
UDMACH12SSEL	Output Selection for DMA Channel 12 SREQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS
UDMACH12BSEL	Output Selection for DMA Channel 12 REQ DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS
UDMACH13SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH13BSEL	Output Selection for DMA Channel 13 REQ
UDMACH14SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH14BSEL	Output Selection for DMA Channel 14 REQ
UDMACH15SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH15BSEL	Output Selection for DMA Channel 15 REQ
UDMACH16SSEL	Output Selection for DMA Channel 16 SREQ
UDMACH16BSEL	Output Selection for DMA Channel 16 REQ
UDMACH17SSEL	Output Selection for DMA Channel 17 SREQ
UDMACH17BSEL	Output Selection for DMA Channel 17 REQ
UDMACH18SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH18BSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH19SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH19BSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH20SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH20BSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH21SSEL	Output Selection for DMA Channel 21 SREQ
UDMACH21BSEL	Output Selection for DMA Channel 21 REQ
UDMACH22SSEL	Output Selection for DMA Channel 22 SREQ
UDMACH22BSEL	Output Selection for DMA Channel 22 REQ
UDMACH23SSEL	Output Selection for DMA Channel 23 SREQ
UDMACH23BSEL	Output Selection for DMA Channel 23 REQ
UDMACH24SSEL	Output Selection for DMA Channel 24 SREQ
UDMACH24BSEL	Output Selection for DMA Channel 24 REQ
UDMACH25SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH25BSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH26SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH26BSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH27SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH27BSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH28SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH28BSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH29SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH29BSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH30SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH30BSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH31SSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
UDMACH31BSEL	Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.