Module cc2650::crypto

Crypto core with DMA capability and local key storage

Modules

aesauthlen	AES Authentication Length
aesctl	AES Input/Output Buffer Control
aesdatain0	AES Data Input/Output 0
aesdatain1	AES Data Input/Output 1
aesdatain2	AES Data Input/Output 2
aesdatain3	Data Input/Output
aesdatalen0	Crypto Data Length LSW
aesdatalen1	Crypto Data Length MSW
aesdataout0	Data Input/Output
aesdataout1	AES Data Input/Output 3
aesdataout2	AES Data Input/Output 2
aesdataout3	AES Data Input/Output 3
aesiv	AES Initialization Vector
aeskey2	Clear AES_KEY2/GHASH Key
aeskey3	Clear AES_KEY3
aestagout	AES Tag Output
algsel	Master Algorithm Select This register configures the internal destination of the DMA controller.
dmabuscfg	DMA Controller Master Configuration
dmach0ctl	DMA Channel 0 Control
dmach0len	DMA Channel 0 Length
dmach0extaddr	DMA Channel 0 External Address
dmach1ctl	DMA Channel 1 Control
dmach1extaddr	DMA Channel 1 External Address
dmach1len	DMA Channel 1 Length
dmahwver	DMA Controller Version
dmaporterr	DMA Controller Port Error
dmaprotctl	Master Protection Control
dmastat	DMA Controller Status
dmaswreset	DMA Controller Software Reset
hwver	CTRL Module Version
irqclr	Interrupt Clear
irqen	Interrupt Enable
irqset	Interrupt Set
irqstat	Interrupt Status
irqtype	Control Interrupt Configuration
keyreadarea	Key Read Area
keysize	Key Size This register defines the size of the keys that are written with DMA.
keywritearea	Key Write Area
keywrittenarea	Key Written Area Status This register shows which areas of the key store RAM contain valid written keys. When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first. This can be done by writing this register before the new key is written to the key store memory. Attempting to write to a key area that already contains a valid key is not allowed and will result in an error.
swreset	Software Reset

Structs

AESAUTHLEN	AES Authentication Length
AESCTL	AES Input/Output Buffer Control
AESDATAIN0	AES Data Input/Output 0
AESDATAIN1	AES Data Input/Output 1
AESDATAIN2	AES Data Input/Output 2
AESDATAIN3	Data Input/Output
AESDATALEN0	Crypto Data Length LSW
AESDATALEN1	Crypto Data Length MSW
AESDATAOUT0	Data Input/Output
AESDATAOUT1	AES Data Input/Output 3
AESDATAOUT2	AES Data Input/Output 2
AESDATAOUT3	AES Data Input/Output 3
AESIV	AES Initialization Vector
AESKEY2	Clear AES_KEY2/GHASH Key
AESKEY3	Clear AES_KEY3
AESTAGOUT	AES Tag Output
ALGSEL	Master Algorithm Select This register configures the internal destination of the DMA controller.
DMABUSCFG	DMA Controller Master Configuration
DMACH0CTL	DMA Channel 0 Control
DMACH0LEN	DMA Channel 0 Length
DMACH0EXTADDR	DMA Channel 0 External Address
DMACH1CTL	DMA Channel 1 Control
DMACH1EXTADDR	DMA Channel 1 External Address
DMACH1LEN	DMA Channel 1 Length
DMAHWVER	DMA Controller Version
DMAPORTERR	DMA Controller Port Error
DMAPROTCTL	Master Protection Control
DMASTAT	DMA Controller Status
DMASWRESET	DMA Controller Software Reset
HWVER	CTRL Module Version
IRQCLR	Interrupt Clear
IRQEN	Interrupt Enable
IRQSET	Interrupt Set
IRQSTAT	Interrupt Status
IRQTYPE	Control Interrupt Configuration
KEYREADAREA	Key Read Area
KEYSIZE	Key Size This register defines the size of the keys that are written with DMA.
KEYWRITEAREA	Key Write Area
KEYWRITTENAREA	Key Written Area Status This register shows which areas of the key store RAM contain valid written keys. When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first. This can be done by writing this register before the new key is written to the key store memory. Attempting to write to a key area that already contains a valid key is not allowed and will result in an error.
RegisterBlock	Register block
SWRESET	Software Reset