[−][src]Module cc2650::cpu_itm::tcr
Trace Control Use this register to configure and control ITM transfers. This register can only be written in privilege mode. DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is controlled by DWTENA. If DWT requires timestamping, the TSENA bit must be set.
Structs
| ATBIDR | Value of the field |
| BUSYR | Value of the field |
| DWTENAR | Value of the field |
| ITMENAR | Value of the field |
| R | Value read from the register |
| RESERVED5R | Value of the field |
| RESERVED10R | Value of the field |
| RESERVED24R | Value of the field |
| SWOENAR | Value of the field |
| SYNCENAR | Value of the field |
| TSENAR | Value of the field |
| W | Value to write to the register |
| _ATBIDW | Proxy |
| _BUSYW | Proxy |
| _DWTENAW | Proxy |
| _ITMENAW | Proxy |
| _RESERVED5W | Proxy |
| _RESERVED10W | Proxy |
| _RESERVED24W | Proxy |
| _SWOENAW | Proxy |
| _SYNCENAW | Proxy |
| _TSENAW | Proxy |
| _TSPRESCALEW | Proxy |
Enums
| TSPRESCALER | Possible values of the field |
| TSPRESCALEW | Values that can be written to the field |