Module cc2650::prcm

Power, Reset and Clock Management

Modules

clkloadctl	Load PRCM Settings To CLKCTRL Power Domain
cpuclkdiv	Internal. Only to be used through TI provided API.
gpioclkgds	GPIO Clock Gate For Deep Sleep Mode
gpioclkgr	GPIO Clock Gate For Run Mode
gpioclkgs	GPIO Clock Gate For Sleep Mode
gptclkdiv	GPT Scalar
gptclkgds	GPT Clock Gate For Deep Sleep Mode
gptclkgr	GPT Clock Gate For Run Mode
gptclkgs	GPT Clock Gate For Sleep Mode
i2cclkgr	I2C Clock Gate For Run Mode
i2cclkgs	I2C Clock Gate For Sleep Mode
i2cclkgds	I2C Clock Gate For Deep Sleep Mode
i2sclkgr	I2S Clock Gate For Run Mode
i2sclkgs	I2S Clock Gate For Sleep Mode
i2sclkgds	I2S Clock Gate For Deep Sleep Mode
i2sbclksel	I2S Clock Control
i2sclkctl	I2S Clock Control
i2smclkdiv	MCLK Division Ratio
i2sbclkdiv	BCLK Division Ratio
i2swclkdiv	WCLK Division Ratio
infrclkdivds	Infrastructure Clock Division Factor For DeepSleep Mode
infrclkdivr	Infrastructure Clock Division Factor For Run Mode
infrclkdivs	Infrastructure Clock Division Factor For Sleep Mode
pdctl0	Power Domain Control
pdctl0rfc	RFC Power Domain Control
pdctl0serial	SERIAL Power Domain Control
pdctl0periph	PERIPH Power Domain Control
pdctl1	Power Domain Control
pdctl1cpu	CPU Power Domain Direct Control
pdctl1rfc	RFC Power Domain Direct Control
pdctl1vims	VIMS Mode Direct Control
pdstat0	Power Domain Status
pdstat0rfc	RFC Power Domain Status
pdstat0serial	SERIAL Power Domain Status
pdstat0periph	PERIPH Power Domain Status
pdstat1	Power Manager Status
pdstat1bus	BUS Power Domain Direct Read Status
pdstat1rfc	RFC Power Domain Direct Read Status
pdstat1cpu	CPU Power Domain Direct Read Status
pdstat1vims	VIMS Mode Direct Read Status
perbusdmaclkdiv	Internal. Only to be used through TI provided API.
pwrprofstat	Power Profiler Register
ramreten	Memory Retention Control
rfcbits	Control To RFC
rfcclkg	RFC Clock Gate
rfcmodehwopt	Allowed RFC Modes
rfcmodesel	Selected RFC Mode
secdmaclkgds	TRNG, CRYPTO And UDMA Clock Gate For Deep Sleep Mode
secdmaclkgr	TRNG, CRYPTO And UDMA Clock Gate For Run Mode
secdmaclkgs	TRNG, CRYPTO And UDMA Clock Gate For Sleep Mode
ssiclkgds	SSI Clock Gate For Deep Sleep Mode
ssiclkgr	SSI Clock Gate For Run Mode
ssiclkgs	SSI Clock Gate For Sleep Mode
swreset	SW Initiated Resets
uartclkgds	UART Clock Gate For Deep Sleep Mode
uartclkgr	UART Clock Gate For Run Mode
uartclkgs	UART Clock Gate For Sleep Mode
vdctl	MCU Voltage Domain Control
vimsclkg	VIMS Clock Gate
warmreset	WARM Reset Control And Status

Structs

CLKLOADCTL	Load PRCM Settings To CLKCTRL Power Domain
CPUCLKDIV	Internal. Only to be used through TI provided API.
GPIOCLKGDS	GPIO Clock Gate For Deep Sleep Mode
GPIOCLKGR	GPIO Clock Gate For Run Mode
GPIOCLKGS	GPIO Clock Gate For Sleep Mode
GPTCLKDIV	GPT Scalar
GPTCLKGDS	GPT Clock Gate For Deep Sleep Mode
GPTCLKGR	GPT Clock Gate For Run Mode
GPTCLKGS	GPT Clock Gate For Sleep Mode
I2CCLKGR	I2C Clock Gate For Run Mode
I2CCLKGS	I2C Clock Gate For Sleep Mode
I2CCLKGDS	I2C Clock Gate For Deep Sleep Mode
I2SCLKGR	I2S Clock Gate For Run Mode
I2SCLKGS	I2S Clock Gate For Sleep Mode
I2SCLKGDS	I2S Clock Gate For Deep Sleep Mode
I2SBCLKSEL	I2S Clock Control
I2SCLKCTL	I2S Clock Control
I2SMCLKDIV	MCLK Division Ratio
I2SBCLKDIV	BCLK Division Ratio
I2SWCLKDIV	WCLK Division Ratio
INFRCLKDIVDS	Infrastructure Clock Division Factor For DeepSleep Mode
INFRCLKDIVR	Infrastructure Clock Division Factor For Run Mode
INFRCLKDIVS	Infrastructure Clock Division Factor For Sleep Mode
PDCTL0	Power Domain Control
PDCTL0RFC	RFC Power Domain Control
PDCTL0SERIAL	SERIAL Power Domain Control
PDCTL0PERIPH	PERIPH Power Domain Control
PDCTL1	Power Domain Control
PDCTL1CPU	CPU Power Domain Direct Control
PDCTL1RFC	RFC Power Domain Direct Control
PDCTL1VIMS	VIMS Mode Direct Control
PDSTAT0	Power Domain Status
PDSTAT0RFC	RFC Power Domain Status
PDSTAT0SERIAL	SERIAL Power Domain Status
PDSTAT0PERIPH	PERIPH Power Domain Status
PDSTAT1	Power Manager Status
PDSTAT1BUS	BUS Power Domain Direct Read Status
PDSTAT1RFC	RFC Power Domain Direct Read Status
PDSTAT1CPU	CPU Power Domain Direct Read Status
PDSTAT1VIMS	VIMS Mode Direct Read Status
PERBUSDMACLKDIV	Internal. Only to be used through TI provided API.
PWRPROFSTAT	Power Profiler Register
RAMRETEN	Memory Retention Control
RFCBITS	Control To RFC
RFCCLKG	RFC Clock Gate
RFCMODEHWOPT	Allowed RFC Modes
RFCMODESEL	Selected RFC Mode
RegisterBlock	Register block
SECDMACLKGDS	TRNG, CRYPTO And UDMA Clock Gate For Deep Sleep Mode
SECDMACLKGR	TRNG, CRYPTO And UDMA Clock Gate For Run Mode
SECDMACLKGS	TRNG, CRYPTO And UDMA Clock Gate For Sleep Mode
SSICLKGDS	SSI Clock Gate For Deep Sleep Mode
SSICLKGR	SSI Clock Gate For Run Mode
SSICLKGS	SSI Clock Gate For Sleep Mode
SWRESET	SW Initiated Resets
UARTCLKGDS	UART Clock Gate For Deep Sleep Mode
UARTCLKGR	UART Clock Gate For Run Mode
UARTCLKGS	UART Clock Gate For Sleep Mode
VDCTL	MCU Voltage Domain Control
VIMSCLKG	VIMS Clock Gate
WARMRESET	WARM Reset Control And Status