Module cc2650::cpu_itm

Cortex-M's Instrumentation Trace Macrocell (ITM)

Modules

lar	Lock Access This register is used to prevent write accesses to the Control Registers: TER, TPR and TCR.
lsr	Lock Status Use this register to enable write accesses to the Control Register.
stim0	Stimulus Port 0
stim1	Stimulus Port 1
stim2	Stimulus Port 2
stim3	Stimulus Port 3
stim4	Stimulus Port 4
stim5	Stimulus Port 5
stim6	Stimulus Port 6
stim7	Stimulus Port 7
stim8	Stimulus Port 8
stim9	Stimulus Port 9
stim10	Stimulus Port 10
stim11	Stimulus Port 11
stim12	Stimulus Port 12
stim13	Stimulus Port 13
stim14	Stimulus Port 14
stim15	Stimulus Port 15
stim16	Stimulus Port 16
stim17	Stimulus Port 17
stim18	Stimulus Port 18
stim19	Stimulus Port 19
stim20	Stimulus Port 20
stim21	Stimulus Port 21
stim22	Stimulus Port 22
stim23	Stimulus Port 23
stim24	Stimulus Port 24
stim25	Stimulus Port 25
stim26	Stimulus Port 26
stim27	Stimulus Port 27
stim28	Stimulus Port 28
stim29	Stimulus Port 29
stim30	Stimulus Port 30
stim31	Stimulus Port 31
tcr	Trace Control Use this register to configure and control ITM transfers. This register can only be written in privilege mode. DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is controlled by DWTENA. If DWT requires timestamping, the TSENA bit must be set.
ter	Trace Enable Use the Trace Enable Register to generate trace data by writing to the corresponding stimulus port. Note: Privileged writes are accepted to this register if TCR.ITMENA is set. User writes are accepted to this register if TCR.ITMENA is set and the appropriate privilege mask is cleared. Privileged access to the stimulus ports enables an RTOS kernel to guarantee instrumentation slots or bandwidth as required.
tpr	Trace Privilege This register is used to enable an operating system to control which stimulus ports are accessible by user code. This register can only be used in privileged mode.

Structs

LAR	Lock Access This register is used to prevent write accesses to the Control Registers: TER, TPR and TCR.
LSR	Lock Status Use this register to enable write accesses to the Control Register.
RegisterBlock	Register block
STIM0	Stimulus Port 0
STIM1	Stimulus Port 1
STIM2	Stimulus Port 2
STIM3	Stimulus Port 3
STIM4	Stimulus Port 4
STIM5	Stimulus Port 5
STIM6	Stimulus Port 6
STIM7	Stimulus Port 7
STIM8	Stimulus Port 8
STIM9	Stimulus Port 9
STIM10	Stimulus Port 10
STIM11	Stimulus Port 11
STIM12	Stimulus Port 12
STIM13	Stimulus Port 13
STIM14	Stimulus Port 14
STIM15	Stimulus Port 15
STIM16	Stimulus Port 16
STIM17	Stimulus Port 17
STIM18	Stimulus Port 18
STIM19	Stimulus Port 19
STIM20	Stimulus Port 20
STIM21	Stimulus Port 21
STIM22	Stimulus Port 22
STIM23	Stimulus Port 23
STIM24	Stimulus Port 24
STIM25	Stimulus Port 25
STIM26	Stimulus Port 26
STIM27	Stimulus Port 27
STIM28	Stimulus Port 28
STIM29	Stimulus Port 29
STIM30	Stimulus Port 30
STIM31	Stimulus Port 31
TCR	Trace Control Use this register to configure and control ITM transfers. This register can only be written in privilege mode. DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is controlled by DWTENA. If DWT requires timestamping, the TSENA bit must be set.
TER	Trace Enable Use the Trace Enable Register to generate trace data by writing to the corresponding stimulus port. Note: Privileged writes are accepted to this register if TCR.ITMENA is set. User writes are accepted to this register if TCR.ITMENA is set and the appropriate privilege mask is cleared. Privileged access to the stimulus ports enables an RTOS kernel to guarantee instrumentation slots or bandwidth as required.
TPR	Trace Privilege This register is used to enable an operating system to control which stimulus ports are accessible by user code. This register can only be used in privileged mode.