Struct cc2538::rfcore_sfr::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub mtcspcfg: MTCSPCFG,
    pub mtctrl: MTCTRL,
    pub mtirqm: MTIRQM,
    pub mtirqf: MTIRQF,
    pub mtmsel: MTMSEL,
    pub mtm0: MTM0,
    pub mtm1: MTM1,
    pub mtmovf2: MTMOVF2,
    pub mtmovf1: MTMOVF1,
    pub mtmovf0: MTMOVF0,
    pub rfdata: RFDATA,
    pub rferrf: RFERRF,
    pub rfirqf1: RFIRQF1,
    pub rfirqf0: RFIRQF0,
    pub rfst: RFST,
}

Register block

Fields

mtcspcfg: MTCSPCFG

0x00 - MAC Timer event configuration

mtctrl: MTCTRL

0x04 - MAC Timer control register

mtirqm: MTIRQM

0x08 - MAC Timer interrupt mask

mtirqf: MTIRQF

0x0c - MAC Timer interrupt flags

mtmsel: MTMSEL

0x10 - MAC Timer multiplex select

mtm0: MTM0

0x14 - MAC Timer multiplexed register 0

mtm1: MTM1

0x18 - MAC Timer multiplexed register 1

mtmovf2: MTMOVF2

0x1c - MAC Timer multiplexed overflow register 2

mtmovf1: MTMOVF1

0x20 - MAC Timer multiplexed overflow register 1

mtmovf0: MTMOVF0

0x24 - MAC Timer multiplexed overflow register 0

rfdata: RFDATA

0x28 - The TX FIFO and RX FIFO may be accessed through this register. Data is written to the TX FIFO when writing to the RFD register. Data is read from the RX FIFO when the RFD register is read. The XREG registers RXFIFOCNT and TXFIFOCNT provide information on the amount of data in the FIFOs. The FIFO contents can be cleared by issuing SFLUSHRX and SFLUSHTX.

rferrf: RFERRF

0x2c - RF error interrupt flags

rfirqf1: RFIRQF1

0x30 - RF interrupt flags

rfirqf0: RFIRQF0

0x34 - RF interrupt flags

rfst: RFST

0x38 - RF CSMA-CA/strobe processor