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#[doc = "Reader of register ADCCON2"] pub type R = crate::R<u32, super::ADCCON2>; #[doc = "Writer for register ADCCON2"] pub type W = crate::W<u32, super::ADCCON2>; #[doc = "Register ADCCON2 `reset()`'s with value 0"] impl crate::ResetValue for super::ADCCON2 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `Reserved32`"] pub type RESERVED32_R = crate::R<u32, u32>; #[doc = "Write proxy for field `Reserved32`"] pub struct RESERVED32_W<'a> { w: &'a mut W, } impl<'a> RESERVED32_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u32) -> &'a mut W { self.w.bits = (self.w.bits & !(0x00ff_ffff << 8)) | (((value as u32) & 0x00ff_ffff) << 8); self.w } } #[doc = "Reader of field `SREF`"] pub type SREF_R = crate::R<u8, u8>; #[doc = "Write proxy for field `SREF`"] pub struct SREF_W<'a> { w: &'a mut W, } impl<'a> SREF_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 6)) | (((value as u32) & 0x03) << 6); self.w } } #[doc = "Reader of field `SDIV`"] pub type SDIV_R = crate::R<u8, u8>; #[doc = "Write proxy for field `SDIV`"] pub struct SDIV_W<'a> { w: &'a mut W, } impl<'a> SDIV_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 4)) | (((value as u32) & 0x03) << 4); self.w } } #[doc = "Reader of field `SCH`"] pub type SCH_R = crate::R<u8, u8>; #[doc = "Write proxy for field `SCH`"] pub struct SCH_W<'a> { w: &'a mut W, } impl<'a> SCH_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x0f) | ((value as u32) & 0x0f); self.w } } impl R { #[doc = "Bits 8:31 - 31:8\\] This register is 8 bits in a 32-bit address space."] #[inline(always)] pub fn reserved32(&self) -> RESERVED32_R { RESERVED32_R::new(((self.bits >> 8) & 0x00ff_ffff) as u32) } #[doc = "Bits 6:7 - 7:6\\] Selects reference voltage used for the sequence of conversions 00: Internal reference 01: External reference on AIN7 pin 10: AVDD5 pin 11: External reference on AIN6-AIN7 differential input"] #[inline(always)] pub fn sref(&self) -> SREF_R { SREF_R::new(((self.bits >> 6) & 0x03) as u8) } #[doc = "Bits 4:5 - 5:4\\] Sets the decimation rate for channels included in the sequence of conversions. The decimation rate also determines the resolution and time required to complete a conversion. 00: 64 decimation rate (7 bits ENOB setting) 01: 128 decimation rate (9 bits ENOB setting) 10: 256 decimation rate (10 bits ENOB setting) 11: 512 decimation rate (12 bits ENOB setting)"] #[inline(always)] pub fn sdiv(&self) -> SDIV_R { SDIV_R::new(((self.bits >> 4) & 0x03) as u8) } #[doc = "Bits 0:3 - 3:0\\] Sequence channel select Selects the end of the sequence A sequence can either be from AIN0 to AIN7 (SCH <= 7) or from differential input AIN0-AIN1 to AIN6-AIN7 (8 <= SCH <= 11). For other settings, only one conversions is performed. When read, these bits indicate the channel number on which a conversion is ongoing: 0000: AIN0 0001: AIN1 0010: AIN2 0011: AIN3 0100: AIN4 0101: AIN5 0110: AIN6 0111: AIN7 1000: AIN0-AIN1 1001: AIN2-AIN3 1010: AIN4-AIN5 1011: AIN6-AIN7 1100: GND 1101: Reserved 1110: Temperature sensor 1111: VDD/3"] #[inline(always)] pub fn sch(&self) -> SCH_R { SCH_R::new((self.bits & 0x0f) as u8) } } impl W { #[doc = "Bits 8:31 - 31:8\\] This register is 8 bits in a 32-bit address space."] #[inline(always)] pub fn reserved32(&mut self) -> RESERVED32_W { RESERVED32_W { w: self } } #[doc = "Bits 6:7 - 7:6\\] Selects reference voltage used for the sequence of conversions 00: Internal reference 01: External reference on AIN7 pin 10: AVDD5 pin 11: External reference on AIN6-AIN7 differential input"] #[inline(always)] pub fn sref(&mut self) -> SREF_W { SREF_W { w: self } } #[doc = "Bits 4:5 - 5:4\\] Sets the decimation rate for channels included in the sequence of conversions. The decimation rate also determines the resolution and time required to complete a conversion. 00: 64 decimation rate (7 bits ENOB setting) 01: 128 decimation rate (9 bits ENOB setting) 10: 256 decimation rate (10 bits ENOB setting) 11: 512 decimation rate (12 bits ENOB setting)"] #[inline(always)] pub fn sdiv(&mut self) -> SDIV_W { SDIV_W { w: self } } #[doc = "Bits 0:3 - 3:0\\] Sequence channel select Selects the end of the sequence A sequence can either be from AIN0 to AIN7 (SCH <= 7) or from differential input AIN0-AIN1 to AIN6-AIN7 (8 <= SCH <= 11). For other settings, only one conversions is performed. When read, these bits indicate the channel number on which a conversion is ongoing: 0000: AIN0 0001: AIN1 0010: AIN2 0011: AIN3 0100: AIN4 0101: AIN5 0110: AIN6 0111: AIN7 1000: AIN0-AIN1 1001: AIN2-AIN3 1010: AIN4-AIN5 1011: AIN6-AIN7 1100: GND 1101: Reserved 1110: Temperature sensor 1111: VDD/3"] #[inline(always)] pub fn sch(&mut self) -> SCH_W { SCH_W { w: self } } }