Module cc2538::gpio_c::mis

The MIS register is the masked interrupt status register. Bits read high in MIS reflect the status of input lines triggering an interrupt. Bits read as low indicate that either no interrupt has been generated, or the interrupt is masked. MIS is the state of the interrupt after masking.

Structs

MIS_W	Write proxy for field MIS
RESERVED32_W	Write proxy for field Reserved32

Type Definitions

MIS_R	Reader of field MIS
R	Reader of register MIS
RESERVED32_R	Reader of field Reserved32
W	Writer for register MIS