[−][src]Module cc2538::sys_ctrl
System Control.
Modules
| cld | This register controls the clock loss detection feature. |
| clock_ctrl | The clock control register handels clock settings in the CC2538. The settings in CLOCK_CTRL do not always reflect the current chip status which is found in CLOCK_STA register. |
| clock_sta | Clock status register This register reflects the current chip status. |
| dcgcgpt | This register defines the module clocks for GPT[3:0] when the CPU is in PM0. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| dcgci2c | This register defines the module clocks for I2C when the CPU is in PM0. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| dcgcrfc | This register defines the module clocks for RF CORE when the CPU is in PM0. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| dcgcsec | This register defines the module clocks for the security module when the CPU is in PM0. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| dcgcssi | This register defines the module clocks for SSI[1:0] when the CPU is in PM0. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| dcgcuart | This register defines the module clocks for UART[1:0] when the CPU is in PM0. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| emuovr | This register defines the emulator override controls for power mode and peripheral clock gate. |
| i_map | This register selects which interrupt map to be used. |
| iwe | This register controls interrupt wake-up. |
| pmctl | This register controls the power mode. Note: The Corresponding PM is not entered before the WFI instruction is asserted. To enter PM1-3 the DEEPSLEEP bit in SYSCTRL must be 1. |
| pwrdbg | Power debug register |
| rcgcgpt | This register defines the module clocks for GPT[3:0] when the CPU is in active (run) mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| rcgci2c | This register defines the module clocks for I2C when the CPU is in active (run) mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| rcgcrfc | This register defines the module clocks for RF CORE when the CPU is in active (run) mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| rcgcsec | This register defines the module clocks for the security module when the CPU is in active (run) mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| rcgcssi | This register defines the module clocks for SSI[1:0] when the CPU is in active (run) mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| rcgcuart | This register defines the module clocks for UART[1:0] when the CPU is in active (run) mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| scgcgpt | This register defines the module clocks for GPT[3:0] when the CPU is in sleep mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| scgci2c | This register defines the module clocks for I2C when the CPU is in sleep mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| scgcrfc | This register defines the module clocks for RF CORE when the CPU is in sleep mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| scgcsec | This register defines the module clocks for the security module when the CPU is in sleep mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| scgcssi | This register defines the module clocks for SSI[1:0] when the CPU is insSleep mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| scgcuart | This register defines the module clocks for UART[1:0] when the CPU is in sleep mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| srcrc | This register controls CRC on state retention. |
| srgpt | This register controls the reset for GPT[3:0]. |
| sri2c | This register controls the reset for I2C. |
| srsec | This register controls the reset for the security module. |
| srssi | This register controls the reset for SSI[1:0]. |
| sruart | This register controls the reset for UART[1:0]. |
Structs
| RegisterBlock | Register block |
Type Definitions
| CLD | This register controls the clock loss detection feature. |
| CLOCK_CTRL | The clock control register handels clock settings in the CC2538. The settings in CLOCK_CTRL do not always reflect the current chip status which is found in CLOCK_STA register. |
| CLOCK_STA | Clock status register This register reflects the current chip status. |
| DCGCGPT | This register defines the module clocks for GPT[3:0] when the CPU is in PM0. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| DCGCI2C | This register defines the module clocks for I2C when the CPU is in PM0. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| DCGCRFC | This register defines the module clocks for RF CORE when the CPU is in PM0. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| DCGCSEC | This register defines the module clocks for the security module when the CPU is in PM0. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| DCGCSSI | This register defines the module clocks for SSI[1:0] when the CPU is in PM0. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| DCGCUART | This register defines the module clocks for UART[1:0] when the CPU is in PM0. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| EMUOVR | This register defines the emulator override controls for power mode and peripheral clock gate. |
| IWE | This register controls interrupt wake-up. |
| I_MAP | This register selects which interrupt map to be used. |
| PMCTL | This register controls the power mode. Note: The Corresponding PM is not entered before the WFI instruction is asserted. To enter PM1-3 the DEEPSLEEP bit in SYSCTRL must be 1. |
| PWRDBG | Power debug register |
| RCGCGPT | This register defines the module clocks for GPT[3:0] when the CPU is in active (run) mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| RCGCI2C | This register defines the module clocks for I2C when the CPU is in active (run) mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| RCGCRFC | This register defines the module clocks for RF CORE when the CPU is in active (run) mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| RCGCSEC | This register defines the module clocks for the security module when the CPU is in active (run) mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| RCGCSSI | This register defines the module clocks for SSI[1:0] when the CPU is in active (run) mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| RCGCUART | This register defines the module clocks for UART[1:0] when the CPU is in active (run) mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| SCGCGPT | This register defines the module clocks for GPT[3:0] when the CPU is in sleep mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| SCGCI2C | This register defines the module clocks for I2C when the CPU is in sleep mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| SCGCRFC | This register defines the module clocks for RF CORE when the CPU is in sleep mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| SCGCSEC | This register defines the module clocks for the security module when the CPU is in sleep mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| SCGCSSI | This register defines the module clocks for SSI[1:0] when the CPU is insSleep mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| SCGCUART | This register defines the module clocks for UART[1:0] when the CPU is in sleep mode. This register setting is don't care for PM1-3, because the system clock is powered down in these modes. |
| SRCRC | This register controls CRC on state retention. |
| SRGPT | This register controls the reset for GPT[3:0]. |
| SRI2C | This register controls the reset for I2C. |
| SRSEC | This register controls the reset for the security module. |
| SRSSI | This register controls the reset for SSI[1:0]. |
| SRUART | This register controls the reset for UART[1:0]. |