[−][src]Module cc2538::i2cs
I2C Slave.
Modules
ctrl | I2C slave control and status This register functions as a control register when written, and a status register when read. |
dr | I2C slave data This register contains the data to be transmitted when in the slave transmit state, and the data received when in the slave receive state. |
icr | I2C slave interrupt clear This register clears the raw interrupt. A read of this register returns no meaningful data. |
imr | I2C slave interrupt mask This register controls whether a raw interrupt is promoted to a controller interrupt. |
mis | I2C slave masked interrupt status This register specifies whether an interrupt was signaled. |
oar | I2C slave own address This register consists of seven address bits that identify the CC2538 I2C device on the I2C bus. |
ris | I2C slave raw interrupt status This register specifies whether an interrupt is pending. |
stat | I2C slave control and status This register functions as a control register when written, and a status register when read. |
Structs
RegisterBlock | Register block |
Type Definitions
CTRL | I2C slave control and status This register functions as a control register when written, and a status register when read. |
DR | I2C slave data This register contains the data to be transmitted when in the slave transmit state, and the data received when in the slave receive state. |
ICR | I2C slave interrupt clear This register clears the raw interrupt. A read of this register returns no meaningful data. |
IMR | I2C slave interrupt mask This register controls whether a raw interrupt is promoted to a controller interrupt. |
MIS | I2C slave masked interrupt status This register specifies whether an interrupt was signaled. |
OAR | I2C slave own address This register consists of seven address bits that identify the CC2538 I2C device on the I2C bus. |
RIS | I2C slave raw interrupt status This register specifies whether an interrupt is pending. |
STAT | I2C slave control and status This register functions as a control register when written, and a status register when read. |