Struct R

pub struct R { /* private fields */ }

Value read from the register

Implementations

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn reserved12(&self) -> RESERVED12R

Bits 12:31 - 31:12] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn eotmis(&self) -> EOTMISR

Bit 11 - 11:11] End of Transmission interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.EOTRIS and the mask setting IMSC.EOTIM.

pub fn oemis(&self) -> OEMISR

Bit 10 - 10:10] Overrun error masked interrupt status: This field returns the masked interrupt state of the overrun interrupt which is the AND product of raw interrupt state RIS.OERIS and the mask setting IMSC.OEIM.

pub fn bemis(&self) -> BEMISR

Bit 9 - 9:9] Break error masked interrupt status: This field returns the masked interrupt state of the break error interrupt which is the AND product of raw interrupt state RIS.BERIS and the mask setting IMSC.BEIM.

pub fn pemis(&self) -> PEMISR

Bit 8 - 8:8] Parity error masked interrupt status: This field returns the masked interrupt state of the parity error interrupt which is the AND product of raw interrupt state RIS.PERIS and the mask setting IMSC.PEIM.

pub fn femis(&self) -> FEMISR

Bit 7 - 7:7] Framing error masked interrupt status: Returns the masked interrupt state of the framing error interrupt which is the AND product of raw interrupt state RIS.FERIS and the mask setting IMSC.FEIM.

pub fn rtmis(&self) -> RTMISR

Bit 6 - 6:6] Receive timeout masked interrupt status: Returns the masked interrupt state of the receive timeout interrupt. The raw interrupt for receive timeout cannot be set unless the mask is set (IMSC.RTIM = 1). This is because the mask acts as an enable for power saving. That is, the same status can be read from RTMIS and RIS.RTRIS.

pub fn txmis(&self) -> TXMISR

Bit 5 - 5:5] Transmit masked interrupt status: This field returns the masked interrupt state of the transmit interrupt which is the AND product of raw interrupt state RIS.TXRIS and the mask setting IMSC.TXIM.

pub fn rxmis(&self) -> RXMISR

Bit 4 - 4:4] Receive masked interrupt status: This field returns the masked interrupt state of the receive interrupt which is the AND product of raw interrupt state RIS.RXRIS and the mask setting IMSC.RXIM.

pub fn reserved2(&self) -> RESERVED2R

Bits 2:3 - 3:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn ctsmmis(&self) -> CTSMMISR

Bit 1 - 1:1] Clear to Send (CTS) modem masked interrupt status: This field returns the masked interrupt state of the clear to send interrupt which is the AND product of raw interrupt state RIS.CTSRMIS and the mask setting IMSC.CTSMIM.

pub fn reserved0(&self) -> RESERVED0R

Bit 0 - 0:0] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.