Module cc13x2_cc26x2_pac::aux_sysif::tdcclkctl

TDC Counter Clock Control Controls if the AUX_TDC counter clock source is enabled. TDC counter clock source is configured in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL.

Structs

ACKR	Value of the field
R	Value read from the register
REQR	Value of the field
RESERVED2R	Value of the field
W	Value to write to the register
_ACKW	Proxy
_REQW	Proxy
_RESERVED2W	Proxy